To Test The Multiple-Clock, Multiple-Edge, State Acquisition (Logic Analyzer); Set Up The Equipment - HP 1660 Series Service Manual

Logic analyzers
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To test the multiple-clock, multiple-edge, state
acquisition (logic analyzer)
Testing the multiple-clock, multiple-edge, state acquisition verifies the performance
of the following specifications:
Minimum master to master clock time.
Maximum state acquisition speed.
Setup/Hold time for multiple-clock, multiple-edge, state acquisition.
Minimum clock pulse width.
This test checks two combinations of data using multiple clocks at three selected
setup/hold times.
Equipment Required
Equipment
Pulse Generator
Digitizing Oscilloscope
Adapter
SMA Coax Cable (Qty 3)
Coupler
BNC Test Connector,
6x2 (Qty 4)

Set up the equipment

Turn on the equipment required and the logic analyzer. Let them warm up for
1 1
30 minutes before beginning the test if you have not already done so.
Set up the pulse generator.
2 2
a a Set up the pulse generator according to the following table.
Pulse Generator Setup
Channel 1
Delay: 0 ps
Width: 4.5 ns
High: − 0.9 V
Low: − 1.7 V
b b Disable the pulse generator channel 2 COMP (with the LED off).
Critical Specifications
100 MHz 3.5 ns pulse width, < 600 ps rise time
≥ 6 GHz bandwidth, < 58 ps rise time
SMA(m)-BNC(f)
18 GHz bandwidth
BNC(m)(m)
Channel 2
Doub: 10.0 ns
Width: 3.5 ns
High: − 0.9 V
Low: − 1.7 V
Recommended
Model/Part
HP 8131A option 020
HP 54121T
HP 1250-1200
HP 8120-4948
HP 1250-0216
Period
20 ns
3–35

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