To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)
Connect the logic analyzer
Using the 6-by-2 test connectors, connect the first combination of logic analyzer
1 1
clock and data channels listed in one of the following tables to the pulse generator.
If you are testing an HP 1660A or HP 1661A, you will repeat this test for the second
combination.
Using SMA cables, connect channel 1, channel 2, and trigger of the oscilloscope to
2 2
the pulse generator.
Connect the HP 1660A or HP 1661A Logic Analyzer to the Pulse Generator
Testing
Connect to
Combinations
HP 8131A
Channel 1 Output
1
Pod 1, channel 3
Pod 3, channel 3
Pod 5, channel 3
Pod 7, channel 3
2
Pod 1, channel 11
Pod 3, channel 11
Pod 5, channel 11
Pod 7, channel 11
3–38
Connect to
Connect to
HP 8131A
HP 8131A
Channel 1 Output
Channel 2 Output
Pod 2, channel 3
J-clock
Pod 4, channel 3
N-clock
Pod 6, channel 3
Pod 8, channel 3
Pod 2, channel 11
J-clock
Pod 4, channel 11
N-clock
Pod 6, channel 11
Pod 8, channel 11
Connect to
HP 8131A
Channel 2 Output
M-clock
M-clock