To Test The Multiple-Clock, Multiple-Edge, State Acquisition - HP 16555A Service Manual

To test the multiple-clock, multiple-edge, state acquisition

Testing the multiple-clock, multiple-edge, state acquisition verifies the performance
of the following specifications:
•
Minimum master to master clock time.
•
Maximum state acquisition speed.
•
Setup/Hold time.
•
Minimum clock pulse width.
Multicard modules must be reconfigured as one-card modules for this test.
This test checks a combination of data channels using multiple clocks at three
selected setup/hold times.
Equipment Required
Equipment
Pulse Generator
Digitizing Oscilloscope
Adapter
SMA Coax Cable (Qty 3)
Coupler (Qty 3)
BNC Test Connector, 6x2 (Qty 3)
Set up the equipment
Turn on the equipment required and the logic analyzer. Let them warm up for
1
30 minutes before beginning the test if you have not already done so.
Set up the pulse generator according to the following table.
2
Pulse Generator Setup
Channel 1
Delay: 0 ps
Width: 4.5 ns
High: −0.9 V
Low: −1.7 V
COMP: Disabled
(LED off)
3–30
Critical Specifications
100 MHz 3.5 ns pulse width, <600 ps rise time
≥ 6 GHz bandwidth, <58 ps rise time
SMA(m)-BNC(f)
BNC(m-m)
Channel 2
Doub: 10.0 ns
Width: 3.5 ns
High: −0.9 V
Low: −1.7 V
COMP: Disabled
(LED off)
Recommended
Model/Part
HP 8131A option 020
HP 54750A w/ HP 54751A
HP 1250-1200
HP 8120-4948
HP 1250-0216
Period
20.0 ns