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3.4.7 UART
Two 3.3V logic level asynchronous serial ports, designated UART0 and UART1 are defined by COM-
HPC. Each port has TX and RX signals for data use and RTS# and CTS# signals for optional handshake
/ flow control use. For logic level use, the TX and RX signals are active high and the RTS# and CTS#
signals are active low. Some data sheets omit the trailing '#' signal but the logic level handshake
signals are active low nonetheless. The idle state, or 'mark' state, of the logic level TX line is high, or
3.3V in the COM-HPC case.
These ports may be used directly as logic level asynchronous serial connections between COM-HPC
Module and Carrier based devices, or between COM-HPC Module and Carrier based mezzanine devices
such as certain Mini-PCIe or M.2 cards. Care has to be taken that the logic I/O levels match up.
The UART interfaces on the COMh-sdID is supported by default via the EC (embedded controller). It
can be reconnected to the SOC's PCH's UARTs on request.
COM-HPC
EC (Default) SOC PCH(Optional)
UART0_TX
UART0_TX
UART0_RX
UART0_RX
UART0_RTS# UART0_RTS#
UART0_CTS# UART0_CTS#
UART1_TX
UART1_TX
UART1_RX
UART1_RX
UART1_RTS# UART1_RTS#
UART1_CTS# UART1_CTS#
Table 17: UART interfaces on COMh-sdID
3.4.8 General Purpose SPI interface
COM-HPC Client and Server modules can support a General Purpose SPI interface (GP_SPI) to connect
multiple peripherals.
The COM-HPC GP_SPI interface on the COMh-sdID is handled by the EC (embedded controller).
EC
COM-HPC
EC_GP_SPI_CLK
GP_SPI_CLK
EC_GP_SPI_MOSI
GP_SPI_MOSI
EC_GP_SPI_MISO
GP_SPI_MISO
EC_GP_SPI_CS0#
GP_SPI_CS0#
EC_GP_SPI_CS1#
GP_SPI_CS1#
EC_GP_SPI_CS2#
GP_SPI_CS2#
EC_GP_SPI_CS3#
GP_SPI_CS3#
EC_GP_SPI_ALERT# GP_SPI_ALERT#
Table 18: GP-SPI on COMh-sdID
3.4.9 Boot SPI
The Boot SPI interface is used to support loading all or parts of the system BIOS from a Module or
Carrier based SPI (Serial Peripheral Interface) or SQI (Serial Quad Interface) flash device. The SPI or
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