Interfaces; Pcie - Kontron COMh-sdID User Manual

3.4 Interfaces

3.4.1 PCIe

COM-HPC allows for up to 49 PCIe lanes on the Client Module pin-out, and for up to 65 PCIe lanes on
the Server Module. The PCIe lanes are divided into 5 Groups:
Group 0 Low: PCIe lanes 0:7 and also an additional lane for BMC use
Group 0 High: PCIe lanes 8:15
Group 1: PCIe lanes 16:31
Group 2: PCIe lanes 32:47
Group 3: PCIe lanes 48:63 (Server Module only)
The integrated SoC PCH supports 24x HSIO lanes #0-23 (HSIO) which can be configured as PCIe Gen
3.0 lanes with up to 3 RPC (Root Port Controller), 4 RP (Root Port) per RPC (12 RPs max). The HSIO
PCIe lanes are partly multiplexed with USB3.0 and SATA.
Further information see chapter 3.3.7 High-Speed Interface Overview
COMh Group COMh Lane PCH/HSIO PCIe Lane Lane Config PCIe Gen
0
1
2
3
0 LOW
4
5
6
7
8
9
10
11
0 HIGH
12
13
14
15
Table 12: PCH HSIO usage
In addition the SoC CPU provides 32x PCIe Gen 4.0 lanes.
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HSIO PCIE 0
x2
HSIO PCIE 1
x4
HSIO PCIE 2
x2
HSIO PCIE 3
x8
HSIO PCIE 4
x2
HSIO PCIE 5
x4
HSIO PCIE 6
x2
HSIO PCIE 7
HSIO PCIE 8
x2
HSIO PCIE 9
x4
HSIO PCIE 10
x2
HSIO PCIE 11
x8
HSIO PCIE 12
x2
HSIO PCIE 13
x4
HSIO PCIE 14
x2
HSIO PCIE 15
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