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Figure 5: CEI interface
Pin
COM-HPC Signal Name
Type
ETH[0:3]_TX+/TX-
O
ETH[0:3]_RX+/RX-
I
ETH[4:7]_TX+/TX-
O
ETH[4:7]_RX+/RX-
I
ETH0-3_MDIO_DAT
I/O
ETH0-3_MDIO_CLK
O
ETH4-7_MDIO_DAT
I/O
ETH4-7_MDIO_CLK
O
ETH0-3_INT#
I
ETH4-7_INT#
I
ETH0-3_PHY_RST#
O
ETH4-7_PHY_RST#
O
ETH0-3_I2C_DAT
I/O
ETH0-3_I2C_CLK
I/O
ETH4-7_I2C_DAT
I/O
ETH4-7_I2C_CLK
I/O
ETH0-3_PRSNT#
I
ETH4-7_PRSNT#
I
Table 16: Mapping of COM-HPC Server specification to CEI interface
In general the COMh-sdID can support the LAN configurations - enabled by different LEK (LAN
Enabling Kit) files - which are aligned with the CEI interface. These are overall described in the
following table.
www.kontron.com
Intel CEI Mapping Description
CEI0_PMD_L[0:3] Ethernet KR ports, transmit output differential pairs.
CEI0_PMD_L[0:3] Ethernet KR ports, receive input differential pairs.
CEI1_PMD_L[0:3] Ethernet KR ports, transmit output differential pairs.
CEI1_PMD_L[0:3] Ethernet KR ports, receive input differential pairs.
Management Data I/O interface mode data signal for serial data transfers between
CEI0_MDIO
the MAC and an external PHY for ETHx ports 0 to 3 .
Clock signal for Management Data I/O interface mode data signal for serial data
CEI0_MDC
transfers between the MAC and an external PHY for ETHx ports 0 to 3.
Management Data I/O interface mode data signal for serial data transfers between
CEI1_MDIO
the MAC and an external PHY for ETHx ports 4 to 7.
Clock signal for Management Data I/O interface mode data signal for serial data
CEI1_MDC
transfers between the MAC and an external PHY for ETHx ports 4 to 7.
CEI0_INT#
Active low interrupt signal from IO Port expanders for ETH ports 0 to 3.
CEI1_INT#
Active low interrupt signal from IO Port expanders for ETH ports 4 to 7.
CEI0_RESET#
Active low output PHY reset signal for ETH ports 0 to 3.
CEI1_RESET#
Active low output PHY reset signal for ETH ports 4 to 7.
I2C data signal of the 2-wire management interface used by the Ethernet KR
controller to access the management registers of an external SFP Module or to
CEI0_SDA
configure the Carrier PHY for ETHx ports 0 to 3 and for serialized status information
(e.g. LED states).
CEI0_SCL
The I2C clock signals associated with ETH0-3 I2C data lines in the row above.
I2C data signal of the 2-wire management interface used by the Ethernet KR
controller to access the management registers of an external SFP Module or to
CEI1_SDA
configure the Carrier PHY for ETHx ports 4 to 7 and for serialized status information
(e.g. LED states).
CEI1_SCL
The I2C clock signals associated with ETH4-7 I2C data lines in the row above.
Carrier pulls this line to GND if there is Carrier hardware present to support Ethernet
CEI0_PRESENT#
KR signaling on ETH0 through ETH3. If the entire KR quad is not supported it should
fill from ETH0 on up.
Carrier pulls this line to GND if there is Carrier hardware present to support Ethernet
CEI1_PRESENT#
KR signaling on ETH4 through ETH7. If the entire KR quad is not supported it should
fill from ETH4 on up.
COMh-sdID User Guide
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