Uart - Kontron COMh-caRP User Manual

COM-HPC Client boards can support following audio interfaces:
Soundwire
HD Audio
COMh-caAPuse SoundWire DMIC and HDAudio/I2S Interface connect to COMh Connectors. Additionally
audio signals are routed to the DP ports. Therefore an extra audio interface is not necessary, if there
is audio output only necessary at the displays.
COMh ADL P
SNDW_DMIC_DAT0 GPP_S7/SNDW3_DATA/DMIC_DATAA1 Bi-directional PCM audio data
SNDW_DMIC_CLK0 GPP_S6/SNDW3_CLK/DMIC_CLK_A1
SNDW_DMIC_DAT1 GPP_S3/SNDW1_DATA/DMIC_DATAA0 Bi-directional PCM audio data
SNDW_DMIC_CLK1 GPP_S2/SNDW1_DATA/DMIC_CLK_A0 Clock for Soundwire transactions
Table 20: Soundwire Interface on COMh-caAP
COMh
I2S_CLK/SNDW_CLK2/HDA_B CLK
I2S_DIN/SNDW_DAT2/HDA_SDI
I2S_DOUT/SNDW_DAT3/HDA_SDO
I2S_LRCLK/SNDW_CLK3/HDA_SYNC SNDW2_DATA GPP_R1/HDA_SYNC/I2S0_SFRM
I2S_MCLK/HDA_RST#
*configurable via BIOS option
Table 21: optional Soundwire, HDA and I2S Interface on COMh-caAP

3.4.7 UART

Two 3.3V logic level asynchronous serial ports, designated UART0 and UART1 are defined by COM-
HPC. Each port has TX and RX signals for data use and RTS# and CTS# signals for optional handshake
/ flow control use. For logic level use, the TX and RX signals are active high and the RTS# and CTS#
signals are active low. Some data sheets omit the trailing '#' signal but the logic level handshake
signals are active low nonetheless. The idle state, or 'mark' state, of the logic level TX line is high, or
3.3V in the COM-HPC case.
These ports may be used directly as logic level asynchronous serial connections between COM-HPC
Module and Carrier based devices, or between COM-HPC Module and Carrier based mezzanine devices
such as certain Mini-PCIe or M.2 cards. Care has to be taken that the logic I/O levels match up.
The UART interface on COMh-caAP is by default driven from the embedded controller. It can be
reconnected on a custom version to the PCH's UART.
COMh EC (Default) PCH (Optional)
UART0_TX UART0_TX
UART0_RX UART0_RX
UART0_RTS# UART0_RTS# GPP_H13/UART0_CTS#
UART0_CTS# UART0_CTS# GPP_H12/UART0_RTS#
UART1_TX UART1_TX
UART1_RX UART1_RX
UART1_RTS# UART1_RTS# -
UART1_CTS# UART1_CTS# -
Table 22: UART interface on COMh-caAP
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Description
Clock for Soundwire transactions
ADL P SNDW ADL P HDA
SNDW0_CLK GPP_R0/HDA_BCLK/I2S0_SCLK
SNDW0_DATA GPP_R3/HDA_SDI0/I2S0_RXD
SNDW2_CLK GPP_R2/HDA_SDO/I2S0_TXD
- GPP_R4/HDA_RST# I2S_MCLK1_OUT*
GPP_H11/UART0_TXD
GPP_H10/UART0_RXD
GPP_D18/UART1_TXD
GPP_D17/UART1_RXD
ADL P I2S
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