cPCI-MXS64 Technical Reference Manual
3.1.5 Multimedia, History Status
CPLD
Address
READ
n92h*
WRITE
n92h*
Power-up Default
CLRHIS
: When low, clear all history bits. Put this bit to 1 to enable history logging.
WD_LOCK
: When high, lock the state of the enable bit for the digital watchdog
3.1.6 Monitoring Status and I/O Access
CPLD
Address
READ
n93h*
WRITE
n93*h
Power-up Default
I2C_DATA
: I2C data
I2C_CLK
: I2C Clock
IDCHIP
: One-wire clock/data for silicon ID chip
3.1.7 Uart 3 PnP Configuration
CPLD Address
READ
n94*h
CND3
WRITE
n94*h
CND3
Power-up Default
CND3
: When low, decode the base address.
CIS3_[1..0]
: COM port interrupt select.
CBAS3_[1..0]
: COM base address select.
D7
D6
D5
NU
NU
NU
NU
NU
NU
D7
D6
D5
NU
NU
NU
NU
NU
NU
D7
D6
D5
CIS3_1
CIS3_0 CBAS3_
CIS3_1
CIS3_0 CBAS3_
0
0
0
D4
D3
NU
NU
WD_LOCK
NU
NU
WD_LOCK
D4
D3
NU
IDCHIP
NU
IDCHIP
0
D4
D3
CBAS3_0 Reserve
1
CBAS3_0 Reserve
1
0
1
3-4
D2
D1
NU
CLRHIS
NU
CLRHIS
1
D2
D1
D0
NU
I2C_CLK I2C_DATA
NU
I2C_CLK I2C_DATA
0
0
D2
D1
Reserve
Reserve
d
d
Reserve
Reserve
d
d
0
0
D0
1
D0
d
d
1