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COMh-sdID User Guide
The COMh-sdID supports one 1/2.5GBASE-T port and and up to eight KR interfaces.
HSIO lane #16 of the integrated SOC PCH is used as PCIe Gen 3.0 lane for the onboard 1/2.5 GbE
Controller Intel i226 (see chapter 3.3.7 High-Speed Interface Overview).
The Intel® Xeon® D-2700 processor family supports up to two integrated PHY Quads with
1G/2.5G/10G/25G/40G/50G/100G rates (depending on the processor SKU).
Figure 4: D-2700 Ethernet MAC configurations
COM-HPC supports both MDIO and I2C control interfaces for the PHYs to be located on the carrier. The
MDIO and I2C control interfaces are grouped into quads, for KR ports 0:3 and ports 4:7. With COM-HPC
the so-called CEI (Common Electrical Interface) from Intel is introduced for the Ethernet interface. One
CEI interface comprises the Ethernet KR signals as well as the sideband and control signals for one
quad. Two CEI interfaces are supported for two quads.
With CEI the Ethernet sideband and control signals are serialized in order to reduce the overall
required signals between the module and the carrier.
The carrier is to de-serialize these signals using small, low cost I2C based I/O expanders. Details are
presented in the COM-HPC Carrier Board Design Guide.
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