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Power Supply Control Signals
Power supply control settings are set in the BIOS and enable the module to shut down, reset and
wake from standby.
COM-HPC Signal
Pin Description
Power Button
B02
(PWRBTN#)
Power Good
C06
(VIN_PWR_OK)
Reset Button
C02
(RSTBTN#)
Platform Reset
A12
(PLTRST#)
Suspend to RAM
B08
(SUS_S3#)
Suspend to Disk
C08 Indicates system is in Suspend to Disk (S4) or Soft Off (S5) state. Active low output.
(SUS_S4_S5#)
Suspend Clock
A87 32.768 kHz +/- 100 ppm clock used by Carrier peripherals such as M.2 cards in their low power modes.
(SUS_CLK)
PCIe Wake UP
D10 PCI Express wake up signal.
(WAKE0#)
GP Wake UP
D11 General purpose wake up signal. May be used to implement wake-up on PS2 keyboard or mouse activity.
(WAKE1#)
Battery Low
A11
(BATLOW#)
Lid detection
B45
(LID#)
Sleep button
B46
(SLEEP#)
Tamper Signal
B06
(TAMPER#)
No power
D34 Driven hard low on Carrier if system AC power is not present.
(AC_PRESENT)
Resume Reset
B86
(RSMRST_OUT#)
Table 25: Power Supply Control Signals
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A PWRBTN# falling edge signal creates power button event (50 ms ≤ t < 4 s, typical 400 ms) at low level).
Power button events can be used to bring a system out of S5 soft-off and other suspend states, as well as
powering the system down. Pressing the power button for at least four seconds turns off power to the
module Power Button Override.
Indicates that all power supplies to the module are stable within specified ranges. PWR_OK signal goes active
and module internal power supplies are enabled.
PWR_OK can be driven low to prevent module from powering up until the carrier is ready and releases the
signal.
PWR_OK should not be deactivated after the module enters S0 unless there is a power fail condition.
Reset button input. The RSTBTN# may be level sensitive (active low) or may be triggered by the falling edge
of the signal.
There are some situations in which it is desirable for a sustained low state of the RSTBTN# to keep the CPU
Module unit in a reset condition. This situation comes up with large Carrier or module based FPGAs that need
more time to be loaded and configured than the CPU boot time allows. Therefore, COM-HPC Module designs
should either keep the CPU Module in a reset state while RSTBTN# is low, or they should pause the boot
process in an early state while RSTBTN# is low. This can be done by the Module BIOS monitoring the
RSTBTN# line through an I/O port. The BIOS should be paused in an early point, before PCIe and USB
enumerations take place.
Additionally, the Module PLTRST# signal (below) should not be released (driven or pulled high) while the
RSTBTN# is low. For situations when RSTBTN# is not able to reestablish control of the system, VIN_PWR_OK
or a power cycle may be used.
Platform Reset: output from Module to Carrier Board. Active low. Issued by Module chipset and may result
from a low RSTBTN# input, a low VIN_PWR_OK input, a VCC power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module software.
PLTRST# should remain asserted (low) while the RSTBTN# is low.
Indicates system is in Suspend to RAM state. Active low output. An inverted copy of SUS_S3# on the Carrier
Board should be used to enable the non-standby power on a typical ATX supply.
Even in single input supply system implementations (AT mode, no standby input), the SUS_S3# Module
output should be used disable any Carrier voltage regulators when SUS_S3# is low, to prevent bleed leakage
from Carrier circuits into the Module.
Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly transitioning to power saving or power cut-
off ACPI modes.
LID switch.
COM-HPC/Client only: Low active signal used by the ACPI operating system for a LID switch.
Sleep button.
COM-HPC/Client only: Low active signal used by the ACPI operating system to bring the system to sleep state
or to wake it up again.
Tamper or Intrusion detection line on VCC_RTC power well. Carrier hardware pulls this low on a Tamper
event.
This is a buffered copy of the internal Module RSMRST# (Resume Reset, active low) signal. The internal
Module RSMRST# signal is an input to the chipset or SOC and when it transitions from low to high it indicates
that the suspend well power rails are stable.
USB devices on the Carrier that are to be active in S5 / S3 / S0 should not have their 5V supply applied before
RSMRST_OUT# goes high. RSMRST_OUT# shall be a 3.3V CMOS Module output, active in all power states.
COMh-sdID User Guide
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