Rtc; Spurious Tamper Detection When Disabling The Tamper Channel; A Tamper Event Preceding The Tamper Detect Enable Not Detected; Rtc Calendar Registers Are Not Locked Properly - ST STM32F078CB Errata Sheet

STM32F078CB/RB/VB
2.6

RTC

2.6.1

Spurious tamper detection when disabling the tamper channel

Description
If the tamper detection is configured for detecting on falling-edge event (TAMPFLT[1:0]=00
and TAMPxTRG=1) and if the tamper event detection is disabled when the tamper pin is at
high level, a false detection of a tamper event occurs, which may result in the erasure of
backup registers.
Workaround
The false detection of tamper event cannot be avoided. The erasure of the backup
registerscan be avoided by setting the TAMPxNOERASE bit before clearing the TAMPxE
bit, in two separate RTC_TAMPCR write accesses.
2.6.2

A tamper event preceding the tamper detect enable not detected

Description
When the tamper detect is enabled, set in edge detection mode (TAMPFLT[1:0]=00), and
•
set to active rising edge (TAMPxTRG=0): if the tamper input is already high (tamper
event already occurred) at the moment of enabling the tamper detection, the tamper
event may not be detected. The probability of detection increases with the APB
frequency.
•
set to active falling edge (TAMPxTRG=1): if the tamper input is already low (tamper
event already occurred) at the moment of enabling the tamper detection, the tamper
event is not detected.
Workaround
The I/O state should be checked by software in the GPIO registers, after enabling the
tamper detection and before writing sensitive values in the backup registers, in order to
ensure that no active edge occurred before enabling the tamper event detection.
2.6.3

RTC calendar registers are not locked properly

Description
When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR
registers may not be locked after the read of RTC_SSR register. This happens if the read of
RTC_SSR is initiated one APB clock period before the shadow registers are updated. This
can result in a non-consistency of the 3 registers. Similarly, RTC_DR register can be
updated after the read of the RTC_TR register instead of being locked.
Workaround
1. Use BYPSHAD = 1 mode (Bypass shadow registers), or
2. In case BYPSHAD = 0: read SSR again after reading SSR/TR/DR to confirm that SSR
is still the same, otherwise read the values again.
DocID026420 Rev 2
Description of device limitations
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