Wrong Crc Transmitted In Master Mode With Delayed Sck Feedback; Crc Error In Spi Slave Mode If Internal Nss Changes Before Crc; Transfer; Spi Crc Corrupted Upon Dma Transaction Completion By Another - ST STM32F078CB Errata Sheet

STM32F078CB/RB/VB
2.4.3

Wrong CRC transmitted in master mode with delayed SCK feedback

Description
In transmit transaction of the SPI/I
CRC data transmission may be corrupted if the delay of an internal feedback signal derived
from the SCK output (further feedback clock) is greater than one APB clock period. While
data and CRC bit shifting and transfer is based on an internal clock, the CRC progressive
calculation uses the feedback clock. If the delay of the feedback clock is greater than one
APB period, the transmitted CRC value may get wrong.
The main factors contributing to the delay increase are low V
high SCK pin capacitive load and low SCK IO output speed. The SPI communication speed
has no impact.
Workaround
Set the application such as to speed up the SCK edges and / or slow down the APB clock,
through:
• configuring the SCK output GPIO so as to reach lower output impedance
•
minimizing the capacitive load on the SCK output line
• configuring the APB clock speed
2.4.4

CRC error in SPI slave mode if internal NSS changes before CRC

transfer

Description
When the device is configured as SPI slave, the transition of the internal NSS after the
CRCNEXT flag is set may result in wrong CRC value computed by the device and, as a
consequence, a CRC error. As a consequence, the NSS pulse mode cannot be used along
with the CRC function.
Workaround
Prevent the internal NSS signal from changing in the critical period, by configuring the
device to software NSS control if the SPI master pulses the NSS (for example in NSS pulse
mode).
2.4.5

SPI CRC corrupted upon DMA transaction completion by another

peripheral

Description
When the following conditions are all met:
•
CRC function for the SPI is enabled,
•
SPI transaction managed by software (as opposed to DMA) is ongoing and CRCNEXT
flag set,
•
another peripheral using the same DMA channel on which the SPI is mapped
completes a DMA transfer,
the CRCNEXT bit is unexpectedly cleared and the SPI CRC calculation may be corrupted,
setting the CRC error flag.
2
S interface in SPI master mode with CRC enabled, the
DocID026420 Rev 2
Description of device limitations
level, high temperature,
DD
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