AD9776A/AD9778A/AD9779A
Register Name
Sync Control
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Register
Address
Bits
Parameter
0x03
7
DATACLK Delay Mode
0x03
6
Reserved
0x03
5:4
DATACLK Divide<1:0>
0x03
3:0
Data Timing Margin<3:0>
0x04
7:4
DATACLK Delay<3:0>
0x04
3:1
SYNC_O Divide<2:0>
0x04
0
SYNC_O Delay<4>
0x05
7:4
SYNC_O Delay<3:0>
0x05
3:1
SYNC_I Ratio<2:0>
0x05
0
SYNC_I Delay<4>
0x06
7:4
SYNC_I Delay<3:0>
0x06
3:0
SYNC_I Timing Margin<3:0>
0x07
7
SYNC_I Enable
0x07
6
SYNC_O Enable
0x07
5
SYNC_O Triggering Edge
0x07
4:0
Clock State<4:0>
Function
0: manual data timing error correct mode
1: automatic data timing error correct mode
Should always be set to 1.
DATACLK output divider value.
00: divide by 1
01: divide by 2
10: divide by 4
11: divide by 1
Sets the timing margin required to prevent the
Data Timing Error IRQ from being asserted. See
Table 26 for details.
Sets delay of REFCLK in to DATACLK out.
The frequency of the SYNC_O signal is equal to
f
/N, where N is set as follows:
DAC
000: N = 32
001: N = 16
010: N = 8
011: N = 4
100: N = 2
101: N = 1
110: N = undefined
111: N = undefined
This value programs the value of the delay line of
the SYNC_O signal. The delay of SYNC_O is relative
to REFCLK. The delay line resolution is 80 ps per
step.
0000: nominal delay
0001: adds 80 ps delay to SYNC_O
0010: adds 160 ps delay to SYNC_O
...
1111: Adds 2480 ps delay to SYNC_O
This value controls the number of SYNC_I input
pulses required to generate a synchronization
pulse. See Table 27 for details.
This value programs the value of the delay line
of the SYNC_I signal. The delay line resolution is
190 ps per step.
0000: no added delay
0001: adds 190 ps delay to SYNC_I
0010: adds 380 ps delay to SYNC_I
...
1111: adds 2480 ps delay to SYNC_I
1: enables the SYNC_I input
1: enables the SYNC_O output
0: SYNC_O changes on REFCLK falling edge
1: SYNC_O changes on REFCLK rising edge
This value determines the state of the internal
clock generation state machine upon
synchronization.
Rev. A | Page 28 of 60
Default
0
0
00
0000
0000
000
00000
000
00000
0
0
0
0
0
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