Digital Input Data Timing Specifications; Ac Specifications; Changes To Table 3 - Analog Devices AD9776A Manual

Dual 12-/14-/16-bit, 1 gsps, digital-to-analog converters
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AD9776A/AD9778A/AD9779A

DIGITAL INPUT DATA TIMING SPECIFICATIONS

All modes, −40°C to +85°C.
Table 3.
Parameter
Input Data
1
Setup Time
Hold Time
Setup Time
Hold Time
Latency
1× Interpolation
2× Interpolation
4× Interpolation
8× Interpolation
Inverse Sync
2
Power-Up Time
1
Timing vs. temperature and data valid keep out windows are delineated in Table 25.
2
Measured from CSB rising edge on Register 0x00, Bit 4 write from 0 to 1. VREF decoupling capacitor equal to 0.1 μF.

AC SPECIFICATIONS

T
to T
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
MIN
MAX
otherwise noted.
Table 4.
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
f
= 100 MSPS, f
DAC
OUT
f
= 200 MSPS, f
DAC
OUT
f
= 400 MSPS, f
DAC
OUT
f
= 800 MSPS, f
DAC
OUT
TWO-TONE INTERMODULATION DISTORTION (IMD)
f
= 200 MSPS, f
DAC
OUT
f
= 400 MSPS, f
DAC
OUT
f
= 400 MSPS, f
DAC
OUT
f
= 800 MSPS, f
DAC
OUT
NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz
TONE SPACING
f
= 200 MSPS, f
DAC
OUT
f
= 400 MSPS, f
DAC
OUT
f
= 800 MSPS, f
DAC
OUT
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
f
= 491.52 MSPS, f
DAC
f
= 491.52 MSPS, f
DAC
W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO
(ACLR), SINGLE CARRIER
f
= 491.52 MSPS, f
DAC
f
= 491.52 MSPS, f
DAC
Downloaded from
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electronic components distributor
Conditions
Input data to DATACLK
Input data to DATACLK
Input data to REFCLK
Input data to REFCLK
With or without modulation
With or without modulation
With or without modulation
With or without modulation
= 20 MHz
= 50 MHz
= 70 MHz
= 70 MHz
= 50 MHz
= 60 MHz
= 80 MHz
= 100 MHz
= 80 MHz
= 80 MHz
= 80 MHz
= 100 MHz
OUT
= 200 MHz
OUT
= 100 MHz
OUT
= 200 MHz
OUT
Min
Typ
3.0
0.0
−0.8
3.7
25
70
146
297
18
260
OUTFs
AD9776A
AD9778A
Min
Typ
Max
Min
82
81
80
85
87
80
75
75
−152
−155
−157.5
76
69
77.5
76
Rev. A | Page 6 of 60
Max
Unit
ns
ns
ns
ns
DACCLK Cycles
DACCLK Cycles
DACCLK Cycles
DACCLK Cycles
DACCLK Cycles
ms
= 20 mA, maximum sample rate, unless
AD9779A
Typ
Max
Min
Typ
Max
82
82
81
82
80
80
85
87
87
91
85
85
81
81
80
81
−155
−158
−159
−160
−160
−161
78
79
73
74
80
81
78
78
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBm/Hz
dBc
dBc
dBc
dBc

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