Driving The Refclk Input - Analog Devices AD9776A Manual

AD9776A/AD9778A/AD9779A
If the optimal band is in the range of 32 to 62 (higher VCO
frequency), refer to Table 23.
Table 23. Setting Optimal PLL Band, When Band Is in the
Higher Range (32 to 62)
If System Startup
Temperature Is
−40°C to −30°C
−30°C to −10°C
−10°C to +15°C
15°C to 55°C
55°C to 85°C
Known Temperature Calibration with Memory
The preceding procedure requires temperature sensing upon
start-up or reset of the device to optimally choose the PLL band
select value that holds over the entire operating temperature
range. If temperature sensing is not available in the system, a
factory calibration at a known temperature is another method
for guaranteeing lock over temperature.
Factory calibration can be performed as follows:
1. The values of N1 (Register 0x09, Bits<6:5>) and N2
(Register 0x09, Bits<4:3>) should be programmed along
with the PLL settings shown in Table 20.
2. Set the PLL band (Register 0x08, Bits<7:2>) to 63 to enable
PLL auto mode.
3. Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x00, Bit 1) to go high. This should occur within
5 ms.
4. Read back the 6-bit PLL band (Register 0x08, Bits<7:2>).
5. Based on the temperature when the PLL auto band select is
performed, store into nonvolatile memory the PLL band
indicated in either Table 22 or Table 23. On system power-
up or restart, load the stored PLL band value into the PLL
band select parameter (Register 0x08, Bits<7:2>).
Set and Forget Device Option
If the PLL band select configuration methods described in
the previous sections cannot be implemented in a particular
system, there may be a screened device option that can satisfy
the system requirements. Analog Devices offers a pair of screened
devices that are guaranteed to maintain PLL lock over the entire
operating temperature range for a predetermined PLL band
select setting. This allows the user to preload a specific PLL
band select value for all devices that holds over temperature.
Downloaded from Elcodis.com electronic components distributor
Set PLL Band as Follows
Set PLL band = readback band + 3
Set PLL band = readback band + 2
Set PLL band = readback band + 1
Set PLL band = readback band
Set PLL band = readback band − 1

DRIVING THE REFCLK INPUT

The REFCLK input requires a low jitter differential drive signal.
The signal level can range from 400 mV p-p differential to
1.6 V p-p differential centered about a 400 mV input common-
mode voltage. Looking at the single-ended inputs, REFCLK+ or
REFCLK−, each input pin can safely swing from 200 mV p-p to
800 mV p-p about the 400 mV common-mode voltage. Although
these input levels are not directly LVDS compatible, REFCLK
can be driven by an offset ac-coupled LVDS signal, as shown in
Figure 72.
LVDS_P_IN
LVDS_N_IN
Figure 72. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 72. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 73.
TTL OR CMOS
CLK INPUT
Figure 73. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating V
It is important to use CVDD18 and CGND for the clock bias
circuit. Any noise or other signal that is coupled onto the clock
is multiplied by the DAC digital input signal and can degrade
DAC performance.
1kΩ
287Ω
Figure 74. REFCLK V
Rev. A | Page 38 of 60
0.1µF
REFCLK+
50Ω
V = 400mV
CM
50Ω
REFCLK–
0.1µF
0.1µF
50Ω
REFCLK+
REFCLK–
50Ω
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V = 400mV
CM
is shown in Figure 74.
CM
V = 400mV
CM
CVDD18
1nF
0.1µF 1nF
CGND
Generator Circuit
CM