Changes To Table 14 - Analog Devices AD9776A Manual

Table 14. SPI Register Description
Register Name
Comm
Digital Control
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Register
Address Bits Parameter
0x00 7 SDIO Bidirectional
0x00 6 LSB/MSB First
0x00 5 Software Reset
0x00 4 Power-Down Mode
0x00 3 Auto Power-Down Enable
0x00 1 PLL Lock Indicator
(Read Only)
0x01 7:6 Interpolation Factor<1:0>
0x01 5:2 Filter Modulation Mode<3:0>
0x01 1 DATACLK Delay<4>
0x01 0 Zero Stuffing Enable
0x02 7 Data Format
0x02 6 Interleaved Data Bus
0x02 5 Real Mode
0x02 4 DATACLK Delay Enable
0x02 3 Inverse Sinc Enable
0x02 2 DATACLK Invert
0x02 1 TxEnable Invert
0x02 0 Q First
Function
0: use SDIO pin as input data only
1: use SDIO as both input and output data
0: first bit of serial data is MSB of data byte
1: first bit of serial data is LSB of data byte
Bit must be written with a 1, then 0 to soft reset SPI
register map.
0: all circuitry is active
1: disable all digital and analog circuitry, only SPI
port is active
Controls auto power-down mode. See the Power-
Down and Sleep Modes section.
0: PLL is not locked
1: PLL is locked
00: 1× interpolation
01: 2× interpolation
10: 4× interpolation
11: 8× interpolation
See Table 19 for filter modes.
Sets delay of REFCLK input to DATACLK output.
0: zero stuffing off
1: zero stuffing on
0: signed binary
1: unsigned binary
0: both P1D and P2D data ports enabled
1: data for both DACs received on P1D data port
0: enable Q path for signal processing
1: disable Q path data (internal Q channel clocks
disabled, I and Q modulators disabled)
Enables the DATACLK delay feature. More details
on this feature are shown in the Optimizing the
Data Input Timing section.
0: inverse sinc filter disabled
1: inverse sinc filter enabled
0: output DATACLK same phase as internal data
sampling clock, DCLK_SMP
1: output DATACLK opposite phase as internal data
sampling clock, DCLK_SMP
Inverts the polarity of Pin 39, the TXENABLE input
pin (also functions as IQSELECT).
0: in interleaved mode, the first byte of a data-word
pair is sent to the I DAC
1: in interleaved mode, the first byte of a data-word
pair is sent to the Q DAC
Rev. A | Page 27 of 60
AD9776A/AD9778A/AD9779A
Default
0
0
0
0
00
0000
0
0
0
0
0
0
0
0