Analog Devices AD9776A Manual page 29

Register Name
PLL Control
Misc. Control
I DAC Control
AUX DAC1 Control
Q DAC Control
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Register
Address Bits Parameter
0x08 7:2 PLL Band Select<5:0>
0x08 1:0 PLL VCO Drive<1:0>
0x09 7 PLL Enable
0x09 6:5 PLL VCO Divide Ratio<1:0>
0x09 4:3 PLL Loop Divide Ratio<1:0>
0x09 2:0 PLL Bias<2:0>
0x0A 7:5 VCO Control Voltage<2:0>
(Read Only)
0x0A 4:0 PLL Loop Bandwidth<4:0>
0x0C 1:0 I DAC Gain Adjustment<9:8>
0x0B 7:0 I DAC Gain Adjustment<7:0>
0x0C 7 I DAC Sleep
0x0C 6 I DAC Power-Down
0x0E 1:0 Auxiliary DAC1 Data<9:8>
0x0D 7:0 Auxiliary DAC1 Data<7:0>
0x0E 7 Auxiliary DAC1 Sign
0x0E 6 Auxiliary DAC1 Current
Direction
0x0E 5 Auxiliary DAC1 Power-Down
0x10 1:0 Q DAC Gain Adjustment<9:8>
0x0F 7:0 Q DAC Gain Adjustment<7:0>
0x10 7 Q DAC Sleep
0x10 6 Q DAC Power-Down
Function
This sets the operating frequency range of the
VCO. For details, see Table 21.
Controls the signal strength of the VCO output. Set
to 11 for optimal performance.
0: PLL off, DAC sample clock is sourced directly by
the REFCLK input.
1: PLL on, DAC clock synthesized internally from
REFCLK input via PLL clock multiplier.
Sets the value of the VCO output divider which
determines the ratio of the VCO output frequency
to the DAC sample clock frequency, f
00: f /f = 1
VCO DACCLK
01: f /f = 2
VCO DACCLK
10: f /f = 4
VCO DACCLK
11: f /f = 8
VCO DACCLK
Sets the value of the DACCLK divider which
determines the ratio of the DAC sample clock
frequency to the REFCLK frequency, f
00: f /f = 2
DACCLK REFCLK
01: f /f = 4
DACCLK REFCLK
10: f /f = 8
DACCLK REFCLK
11: f /f = 16
DACCLK REFCLK
Controls VCO bias current. Set to 011 for optimal
performance.
000 to 111, proportional to voltage at VCO control
voltage input, readback only. A value of 011
indicates the VCO centered in its frequency range.
Controls the bandwidth of the PLL filter. Increasing
the value lowers the loop bandwidth. Set to 01111
for optimal performance.
I DAC 10-bit gain setting word. Bit 9 is the MSB and
Bit 0 is the LSB.
0: I DAC on
1: I DAC off
0: I DAC on
1: I DAC off
AUX DAC1 10-bit output current control word.
Magnitude of the AUX DAC current increases with
increasing value. Bit 9 is the MSB and Bit 0 is the LSB
0: AUX1_P active
1: AUX1_N active
0: source
1: sink
0: AUX DAC1 on
1: AUX DAC1 off
Q DAC 10-bit gain setting word. Bit 9 is the MSB
and Bit 0 is the LSB.
0: Q DAC on
1: Q DAC off
0: Q DAC on
1: Q DAC off
Rev. A | Page 29 of 60
AD9776A/AD9778A/AD9779A
/f .
VCO DACCLK
/f .
DACCLK REFCLK
Default
111001
11
0
10
10
010
000
11111
01
11111001
0
0
00
00000000
0
0
0
01
11111001
0
0