(四) Ddr3 - Alinx AX7102 User Manual

AX7102 User Manual
(四) DDR3
The core board features 1GB of DDR3 memory, implemented using two 512MB
DDR3 devices. The data bandwidth is in 32-bit, comprised of two x16 devices
with a single address/command bus. the target clock speed for FPGA and DDR3
is 800 MHz(Data rate is 1600M). The part number of equipped two DDR3
devices is Micron MT41J256M16HA-125 which is compatible with
MT41K256M16HA-125. Detail information of DDR3 SDRAM is shown in table
2-4-1 below.
Table 2-4-1 DDR3 SDRAM Information
Part P/N Capacity Vender
U5,U6 MT41J256M16HA-125 256M x 16bit Micron
Connections between FPGA and DDR3 are shown in Figure 2-4-1.
U1
U5
Data[31:16] DDR3
(MT41J256M16
HA)
BANK
FPGA
34/35
Addr/control
U6
DDR3
Data[15:0]
(MT41J256M16
HA)
Figure 2-4-1 Connections between FPGA and DDR3
Figure 2-4-2 shows onboard two DDR3 SDRAM.
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