Alinx AX7102 User Manual page 44

Pin Assignment of USB2.0
Net Name
USB_CLKOUT
USB_IFCLK
USB_FLAGA
USB_FLAGB
USB_FLAGC
USB_SLCS
USB_SLWR
USB_SLRD
USB_SLOE
USB_PKTEND
USB_FIFOADR[0]
USB_FIFOADR[1]
USB_FD[0]
USB_FD[1]
USB_FD[2]
USB_FD[3]
USB_FD[4]
USB_FD[5]
USB_FD[6]
USB_FD[7]
USB_FD[8]
USB_FD[9]
USB_FD[10]
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Figure 3-5-2 USB2.0 Onboard
FPGA PIN
U18
Y21
R18
R14
P14
P16
R19
P19
N13
P20
N14
N15
Y22
W20
W19
Y19
Y18
V22
U22
T18
R17
R16
P15
AX7102 User Manual
Comments
12, 24 or 48 MHz Clock Output
Synchronously clock
Programmable slave-FIFO output
status flag signal
Programmable slave-FIFO output
status flag signal
Programmable slave-FIFO output
status flag signal
Slave FIFO chipset select
Slave FIFO write signal
Slave FIFO read signal
Slave FIFO Data Output Enable
Commit the FIFO packet
data to the endpoint
FIFO address０
FIFO address１
USB bidirectional data Bit0
USB bidirectional data Bit1
USB bidirectional data Bit2
USB bidirectional data Bit3
USB bidirectional data Bit4
USB bidirectional data Bit5
USB bidirectional data Bit6
USB bidirectional data Bit7
USB bidirectional data Bit8
USB bidirectional data Bit9
USB bidirectional data Bit10
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