Troubleshooting
Dealing with HPMC (Uncorrectable Error)
HPMC Caused by a Data Cache Parity Error
An HPMC interruption is forced when a data parity
error is detected during a Load instruction to the mem-
ory address space or during a data cache flush opera-
tion.
Table 12 shows an example of the HPMC error infor-
mation retrieved from Stable Storage by the
PIM_INFO command during the Boot Administration
environment.
Table 12
Processor Module Error (Data Cache Parity)
Check Type
CPU State
Cache Check
TLB Check
Bus Check
Assists Check
Assists State
System Responder Address
System Requester Address
System Controller Status
90
SIMM pair identified in this procedure. Return the sys-
tem state (for example, FASTBOOT) to the original
condition.
Word
Value
0x80000000
0x9e000004
0x40000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000nnn