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6-5 SIGNAL TIMING
Signal operation timing is described in the following figure.
To read data by EOC (End of Conversion), when it is set to negative logic, read BCD data, polarity
data, and over data within 4ms from rising (positive) edge (when it is changed from "L" to "H").
To read data after conducting BCD data hold, set the data hold input to "L" and read the required data after 5 ms.
No BCD changes during "L."
When the output prohibit input is set to "L," all the output transistors become OFF.
By controlling the output prohibit input, the BDC data output of parallel connected multiple WGA-670Bs are
sequentially read.
BCD data output
BCD data output
EOC negative logic
EOC negative logic
output
output
Data hold input
Data hold input
Output prohibit input
Output prohibit input
T1:
Data output & EOC signal output time
Number of BCD Output Times/sec
T2, T3: 1ms (min) ............ Relation between BCD signal output and data hold signal input
The [HOLD] signal is read at a timing when the EOC signal output is turned ON.
At this time, if the data hold signal is ON, no data and no EOC signal are output.
T4, T5: 1ms(min) ............. Relation between EOC signal output and output prohibit signal input
The output prohibit signal is read at a timing when the EOC signal output is turned ON.
At this time, if the output prohibit signal is ON, all the data output transistors become OFF.
In addition, no EOC signal is output.
T1/2
T1/2
T1
T1
T2
T2
125
62.5
31.3
15.6
T3
T3
T4
T4
T1(ms)
8
16
32
64
32
T5
T5
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