Bcd Signal Timing - KYOWA WGA-910A Series Instruction Manual

1-7. BCD SIGNAL TIMING

The operation timing is as follows.
Delay time
(Delay time between input and BCD output)
= (Delay time between input and D/A output) + (BCD conversion time)
Delay time between input and D/A output : Max. 3 msec (Analog Filter: none , Moving Average none)
BCD conversion time: Max. 0.5 msec (The number of outputs: 1000 times/sec)
(1) OVER signals
Outputs the OVER signals when the value exceeds the input range or display range. (The OFL1, OFL2, OFL3, or
OFL4 appears.)
The BCD output at this time is the value, immediately before detecting the exceeding value.
(2) POL (negative polarity) signals
Outputs the POL signal when the indicated value is negative (-).
(3) BCD OUTPUT-prohibited signals
When the OUTPUT-prohibited signal is "L (ON)", the transistor outputs are all OFF.
To connect multiple BCD outputs or to select the target channels, use the BCD OUTPUT-prohibited signals.
T1: Data output and EOC signal output time
The number of BCD output (times/sec)
T2, T3: 1 msec (min)
T4, T5: 1 msec (min)
Approx. 1000
Approx. 500
Approx. 250
Approx. 125
Approx. 62.5
Approx. 31.3
Approx. 15.6
Relationship between the EOC signals and DATA HOLDING signals.
Loads the DATA HOLDING signals when the EOC signal is turned ON.
When the DATA HOLDING signal is ON, the product does not output data and
does not output EOC signals.
Relationship between the EOC signals and OUTPUT-prohibited signals.
Loads the OUTPUT-prohibited signals when the EOC signal is turned ON.
When the OUTPUT-prohibited signal is "L (ON)", the data transistor outputs are
all OFF. The product does not output EOC signals.
T1 (msec)
Approx. 1
Approx. 2
Approx. 4
Approx. 8
Approx. 16
Approx. 32
Approx. 64
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