Holtek BS83A04C Manual page 86

I C Bus Data and Acknowledge Signal
2
The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt
of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After
receipt of 8 bits of data, the receiver must transmit an acknowledge signal, level "0", before it can
receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from
the master receiver, then the slave transmitter will release the SDA line to allow the master to send
a STOP signal to release the I
If setup as a transmitter, the slave device must first write the data to be transmitted into the IICD
register. If setup as a receiver, the slave device must read the transmitted data from the IICD register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit
in the IICC1 register to determine if it is to send another data byte, if not then it will release the SDA
line and await the receipt of a STOP signal from the master.
Start
SCL
SDA
SCL
SDA
S=Start (1 bit)
SA=Slave Address (7 bits)
SR=SRW bit (1 bit)
M=Slave device send acknowledge bit (1 bit)
D=Data (8 bits)
A=ACK (RXAK bit for transmitter, TXAK bit for receiver, 1 bit)
P=Stop (1 bit)
S SA SR M
Note: When a slave address is matched, the device must be placed in either the transmit mode and
then write data to the IICD register, or in the receive mode where it must implement a dummy
read from the IICD register to release the SCL line.
Rev. 1.00
4-Key Enhanced Touch I/O Flash MCU
C Bus. The corresponding data will be stored in the IICD register.
2
Slave Address
1 0 1 1 0
Data
1 0 0 1 0 1
D A D A ...... S SA SR M
I C Communication Timing Diagram
2
86
BS83A04C
SRW ACK
1 0 1 0
ACK Stop
0 0
D A D A ...... P
March 24, 2020