Holtek BS83A04C Manual page 82

• IICD Register
Bit 7
Name D7
R/W R/W
POR x
D7~D0: I
Bit 7~0
I C Address Register
2
The IICA register is the location where the 7-bit slave address of the slave device is stored. Bits
7~1 of the IICA register define the device slave address. Bit 0 is not defined. When a master device,
which is connected to the I
register, the slave device will be selected.
• IICA Register
Bit 7
Name IICA6
R/W R/W
POR 0
IICA6~IICA0: I
Bit 7~1
IICA6~IICA0 is the I
Bit 0 Unimplemented, read as "0"
I C Control Registers
2
There are three control registers for the I
is used to control the enable/disable function and to set the data transmission clock frequency.
The IICC1 register contains the relevant flags which are used to indicate the I
status. Another register, IICTOC, is used to control the I
corresponding section.
• IICC0 Register
Bit 7
Name —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
IICDEB1~IICDEB0: I
Bit 3~2
00: No debounce
01: 2 system clock debounce
10/11: 4 system clock debounce
Note that the I
derived from the f
circuit will have no effect and be bypassed.
Bit 1 IICEN: I
0: Disable
1: Enable
The bit is the overall on/off control for the I
to zero to disable the I
and the I
the I
Rev. 1.00
4-Key Enhanced Touch I/O Flash MCU
6 5
D6 D5 D4
R/W R/W R/W
x x
C data register bit 7 ~ bit 0
2
C bus, sends out an address, which matches the slave address in the IICA
2
6 5
IICA5 IICA4 IICA3
R/W R/W R/W
0 0
C slave address
2
C slave address bit 6~bit 0.
2
C interface, IICC0, IICC1 and IICTOC. The IICC0 register
2
6 5
— —
— —
— —
C Debounce Time Selection
2
C debounce circuit will operate normally if the system clock, f
2
clock or the IAMWU bit is equal to 0. Otherwise, the debounce
H
C Enable Control
2
C interface, the SDA and SCL lines will lose their I
2
C operating current will be reduced to a minimum value. When the bit is high
2
C interface is enabled. If the IICEN bit changes from low to high, the contents of
2
82
4 3 2
D3 D2
R/W R/W
x x x
4 3 2
IICA2 IICA1
R/W R/W
0 0 0
C time-out function and is described in the
2
4 3 2
— IICDEB1 IICDEB0
— R/W R/W
— 0 0
C interface. When the IICEN bit is cleared
2
BS83A04C
1 0
D1 D0
R/W R/W
x x
"x": Unknown
1 0
IICA0 —
R/W —
0 —
C communication
2
1 0
IICEN —
R/W —
0 —
, is
SYS
C function
2
March 24, 2020