Holtek BS83A04C Manual page 59

BS83A04C
4-Key Enhanced Touch I/O Flash MCU
flag is generated after a compare match occurs from Comparator A. The CTMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the CTM
output pin. The way in which the CTM output pin changes state are determined by the condition of
the CTIO1 and CTIO0 bits in the CTMC1 register. The CTM output pin can be selected using the
CTIO1 and CTIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the CTM output pin, which is setup after
the CTON bit changes from low to high, is setup using the CTOC bit. Note that if the CTIO1 and
CTIO0 bits are zero then no pin change will take place.
Counter overflow
Counter Value
CCRP=0
0x3FF
CCRP
CCRA
CTON
CTPAU
CTPOL
CCRP Int.
Flag CTMPF
CCRA Int.
Flag CTMAF
CTM O/P Pin
Output pin set to
Output Toggle with
initial Level Low if
CTMAF flag
CTOC=0
Here CTIO [1:0] = 11
Toggle Output select
Note: 1. With CTCCLR=0, a Comparator P match will clear the counter
2. The CTM output pin controlled only by the CTMAF flag
3. The output pin reset to initial state by a CTON bit rising edge
Rev. 1.00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Pause
Output not affected by CTMAF
flag. Remains High until reset
by CTON bit
Note CTIO [1:0] = 10 Active
High Output select
Compare Match Output Mode – CTCCLR=0
59
CTCCLR = 0; CTM [1:0] = 00
Counter
Resume Restart
Stop
Output Inverts
when CTPOL is high
Output Pin
Reset to Initial value
Output controlled by other
pin-shared function
March 24, 2020
Time