Compact Type Tm Operating Modes - Holtek BS83A04C Manual

• CTMDH Register
Bit 7
Name —
R/W —
POR —
Bit 7~2 Unimplemented, read as "0"
Bit 1~0 D9~D8: CTM Counter High Byte Register bit 1 ~ bit 0
CTM 10-bit Counter bit 9 ~ bit 8
• CTMAL Register
Bit 7
Name D7
R/W R/W
POR 0
Bit 7~0 D7~D0: CTM CCRA Low Byte Register bit 7 ~ bit 0
CTM 10-bit CCRA bit 7 ~ bit 0
• CTMAH Register
Bit 7
Name —
R/W —
POR —
Bit 7~2 Unimplemented, read as "0"
Bit 1~0 D9~D8: CTM CCRA High Byte Register bit 1 ~ bit 0
CTM 10-bit CCRA bit 9 ~ bit 8

Compact Type TM Operating Modes

The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and
CTM0 bits in the CTMC1 register.
Compare Match Output Mode
To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the CTCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both CTMAF and CTMPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the CTCCLR bit in the CTMC1 register is high, then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the CTMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore, when
CTCCLR is high no CTMPF interrupt request flag will be generated.
If the CCRA bits are all zero, the counter will overflow when it reaches its maximum 10-bit, 3FF
Hex, value, however here the CTMAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the CTM output pin, will change
state. The CTM output pin condition however only changes state when a CTMAF interrupt request
Rev. 1.00
4-Key Enhanced Touch I/O Flash MCU
6 5 4
— — —
— — —
— — —
6 5 4
D6 D5 D4
R/W R/W R/W
0 0 0
6 5 4
— — —
— — —
— — —
58
BS83A04C
3 2 1
— — D9
— — R
— — 0
3 2 1
D3 D2 D1
R/W R/W R/W
0 0 0
3 2 1
— — D9
— — R/W
— — 0
March 24, 2020
0
D8
R
0
0
D0
R/W
0
0
D8
R/W
0