BS83A04C
4-Key Enhanced Touch I/O Flash MCU
Counter Value
CCRA
CCRP
CTON
CTPAU
CTPOL
CCRP Int.
Flag CTMPF
CCRA Int.
Flag CTMAF
CTM O/P Pin
(CTOC=1)
CTM O/P Pin
(CTOC=0)
PWM Duty Cycle
set by CCRP
Note: 1. Here CTDPX=1 – Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when CTIO[1:0]=00 or 01
4. The CTCCLR bit has no influence on PWM operation
Rev. 1.00
Counter cleared by
CCRA
Pause
PWM Period set by CCRA
PWM Output Mode – CTDPX=1
63
CTDPX = 1; CTM [1:0] = 10
Counter Reset when
CTON returns high
Counter Stop if
Resume
CTON bit low
PWM resumes
operation
Output controlled by
other pin-shared function
Output Inverts
when CTPOL = 1
March 24, 2020
Time
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