Effects Of Dlb And Clkstp On Clock Modes; Clock Generation In The Sample Rate Generator - Texas Instruments TMS320VC5501 Reference Manual

Clock Generation in the Sample Rate Generator

3.2 Clock Generation in the Sample Rate Generator
Table 3−1. Effects of DLB and CLKSTP on Clock Modes
Mode Bit Settings
CLKRM = 1 DLB = 0
(Digital loopback mode disabled)
DLB = 1
(Digital loopback mode enabled)
CLKXM = 1 CLKSTP = 00b or 01b
(Clock stop (SPI) mode disabled)
CLKSTP = 10b or 11b
(Clock stop (SPI) mode enabled)
3-4 Sample Rate Generator of the McBSP
In addition to the three-stage clock divider, the sample rate generator has a
frame-sync pulse detection and clock synchronization module that allows
synchronization of the clock divide down with an incoming frame-sync pulse
on the FSR pin. This feature is enabled or disabled with the GSYNC bit of
SRGR2.
Note:
The clock synchronization provided through the GSYNC bit is not supported
on TMS320VC5501 and TMS320VC5502 devices.
The sample rate generator can produce a clock signal (CLKG) for use by the
receiver, the transmitter, or both. Use of the sample rate generator to drive
clocking is controlled by the clock mode bits (CLKRM and CLKXM) in the pin
control register (PCR). When a clock mode bit is set to 1 (CLKRM = 1 for
reception, CLKXM = 1 for transmission), the corresponding data clock (CLKR
for reception, CLKX for transmission) is driven by the internal sample rate
generator output clock (CLKG).
Note that the effects of CLKRM = 1 and CLKXM = 1 on the McBSP are
partially affected by the use of the digital loopback mode and the clock stop
(SPI) mode, respectively. The digital loopback mode is selected with the DLB
bit of SPCR1. The clock stop mode is selected with the CLKSTP bits of
SPCR1.
When using the sample rate generator as a clock source, make sure the
sample rate generator is enabled (GRST = 1).
Effect
CLKR is an output pin driven by the sample rate
generator output clock (CLKG).
CLKR is an output pin driven by internal CLKX. The
source for CLKX depends on the CLKXM bit.
CLKX is an output pin driven by the sample rate
generator output clock (CLKG).
The McBSP is a master in an SPI system. Internal
CLKX drives internal CLKR and the shift clocks of any
SPI-compliant slave devices in the system. CLKX is
driven by the internal sample rate generator.
SPRU592E