Notes On Differences Between Actual Mcu And Emulator - Renesas M16C/6V User Manual

Notes on Differences between Actual MCU and Emulator:

• Emulator operation differs from mask MCU operation, as listed below:
(1) Reset condition
(2) Initial values of internal resource data at power-on
(3) Internal RAM and ROM capacities, etc.
(4) Ports P0
(5) Writing into pullup control registers 0 and 1 (addresses 03FC
(6) Ports P5
(7) BCLK output disable
(8) Hold control
(9) A/D converter
(10) Status while the program is stopped
IMPORTANT
to P5
0 7
Of the M306V0T-RPD-E's I/O ports, ports P0
through the port emulation circuit inside M306V0T-RPD-E.
Table 1.1 gives the device which uses these ports.
Table 1.1 I/O device used by each of the ports
Port I/O device
P0 -P5 M60074-0111FP
0 7
To write into pullup control registers 0 and 1 (addresses 03FC
is necessary to write the word data from address 03FC
restriction.
- P5
0 3
To enable pullup when setting bit 2 (PUR12) of the pullup register 1 to '1' in single chip mode,
be sure to set the bit 2 (PM02) and bit 7 (PM07) of the processor mode register 0 to '0'. This
is an M306V0T-RPD-E restriction.
To disable the BCLK output, it is necessary to set the BCLK output disable bit (PM07) of
processor mode register 0 (address 0004
(address 03EB ) to '0'. This is an M306V0T-RPD-E restriction.
16
When an 'L' level signal is input to the terminal HOLD and the terminal enters the hold state,
in actuality, ports P0 to P5
0
7, Operation Timing).
A/D converter characteristics differ from actual MCU characteristics because the flexible
cable and other elements are used between the emulation MCU and user's target.
In a system using the PC4701, the loop iteration at the address F8000
maintains the status during program stop. Also, when debug commands are issued to check
or edit memory data, addresses F8000
as work area. For this reason, when the CS0 output is enabled in the microprocessor mode,
the CS0 signal is output.
- P5
0
) to '1' and to set bit 3 of the port P5 direction register
16
enter the hold state one half cycle later than the MCU (see Chapter
2
to F83FF
16 16
( 12 / 48 )
are connected to the user's target system
7
and 03FD
16
and 03FD
16
. This is an M306V0T-RPD-E
16
16
and addresses F6000 to F63FF
16
respectively)
16
respectively), it
16
establishes and
are used
16