Altera Cyclone IV GX Reference Manual page 15

Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 3)
Schematic Signal Name
FSML_WEn
FPGA_CONF_DONE
FPGA_CONFIG_D0
FPGA_nCONFIG
FPGA_nSTATUS
FPGA_DCLK
JTAG_TCK
JTAG_TMS
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
FPGA_MSEL0
FPGA_MSEL1
FPGA_MSEL2
FSML_A1
FSML_A2
FSML_A3
FSML_A4
FSML_A5
FSML_A6
FSML_A7
FSML_A8
FSML_A9
FSML_A10
FSML_A11
FSML_A12
FSML_A13
FSML_A14
FSML_A15
FSML_A16
FSML_A17
FSML_A18
FSML_A19
FSML_A20
FSML_A21
FSML_A22
FSML_A23
FSML_D0
FSML_D1
FSML_D2
© March 2010 Altera Corporation
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I/O EPM2210 EP4CGX15BF14
Standard Pin Number Pin Number
C5
M2
N2
M1
L2
L1
P3
N4
L6
M5
B16
A15
B14
P15
N15
N16
M15
M16
L15
2.5-V L16
K15
K16
J15
J16
H16
H15
G16
G15
F16
F15
E16
E15
D16
D15
C15
C14
A9
A8
B8
A13 FSML bus flash memory write enable
J5 FPGA configuration done
A5 FPGA configuration data
D5 FPGA configuration active
K6 FPGA configuration ready
A4 FPGA configuration clock
B3 FPGA JTAG TCK
A2 FPGA JTAG TMS
A1 FPGA JTAG TDO
— MAX II JTAG TDO
K5 FPGA MSEL0 configuration mode select
N3 FPGA MSEL1 configuration mode select
L3 FPGA MSEL2 configuration mode select
A6 FSML bus address
B6 FSML bus address
C6 FSML bus address
A8 FSML bus address
A7 FSML bus address
M11 FSML bus address
N12 FSML bus address
K10 FSML bus address
L11 FSML bus address
M9 FSML bus address
N10 FSML bus address
N11 FSML bus address
H10 FSML bus address
H12 FSML bus address
N13 FSML bus address
M13 FSML bus address
J13 FSML bus address
K13 FSML bus address
L12 FSML bus address
L13 FSML bus address
K11 FSML bus address
K12 FSML bus address
D13 FSML bus address
D11 FSML bus data
D12 FSML bus data
E10 FSML bus data
Cyclone IV GX Transceiver Starter Board Reference Manual
2–7
Description