Altera Cyclone IV GX Reference Manual page 18

2–10
Figure 2–4. JTAG Chain
Embedded USB-Blaster
USB
PHY
MAX II
EPM240M100
TDI TDO
TDO
2 x 5 Header
Cyclone IV GX Transceiver Starter Board Reference Manual
Downloaded from Elcodis.com electronic components distributor
USB_DISABLE
JTAG
2 x 5 Header
TDI TDO
TCK
GPIO
TMS
GPIO
TDO
GPIO
TDI
GPIO
TMS
TCK
TDI
TMS TCK
JTAG
The Cyclone IV GX FPGA is configured via JTAG using the MAX II configuration
controller design (embedded blaster) as the primary configuration mode. The board
includes a MAX II CPLD EPM2210 System Controller which interfaces directly to the
Cyclone IV GX FPGA for configuration, LCD control, power monitor control, and
other purposes. The MAX II CPLD EPM2210 System Controller contains the required
state machine and control logic to determine the configuration source for the Cyclone
IV GX FPGA.
Table 2–7 lists the Cyclone IV GX configuration modes.
Table 2–7. Cyclone IV GX Configuration Modes
Configuration Mode
Passive Serial (PS)
Active Serial (AS)
Flash Source
JTAG
TMS TCK
EP4CGX15BF14
FPGA
TCK TMS TDI TDO
EPM2210_JTAG_EN
Flash
v
Numonyx
Chapter 2: Board Components
Configuration, Status, and Setup Elements
Flash
128 Mb
SSRAM
18 Mb
MAX II CPLD
PCI Express
EPM2210
(Edge Gold Finger)
System Controller
TCK TMS TDI TDO
TCK TMS TDI TDO
0
0 1
PCIE_JTAG_EN
Device
MAX II EPCS
v
v
v
© March 2010 Altera Corporation
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JTAG
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