I/O Resources - Altera Cyclone IV GX Reference Manual

Chapter 2: Board Components
Featured Device: Cyclone IV GX Device

I/O Resources

Figure 2–2. EP4CGX15BF14 Device I/O Bank Diagram
Table 2–4. Cyclone IV GX Device I/O Pin Count and Usage
Function
Flash, SSRAM, FSML Bus
Gigabit Ethernet
Buttons
LCD
LEDs
Clocks or Oscillators
PCI Express
Passive serial and active serial
configuration
Device I/O Total:
Notes to Table
(1) 60 out of 72 user I/Os are bidirectional I/O pins while the other 12 pins are for clock inputs only.
(2) The total I/O count excludes the transceiver bank.
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Figure 2–2 illustrates the bank organization and I/O count for the EP4CGX15BF14
device in the 169-pin FBGA package.
Number
of Channels
Bank
Name
2 GXB0
Table 2–4 lists the Cyclone IV GX device pin count and usage by function on the
starter board.
I/O Standard
2.5-V CMOS
2.5-V CMOS + LVDS
2.5-V CMOS
2–4:
Bank 6A
EP4CGX15
Bank 5A
Bank
Name
(Note 1)
I/O Count
47 1 DEV_OE
4 —
3 1 DEV_CLRn
1 —
4 1 INIT_DONE, 1 nCEO
7 3 differential clock input pair, 1 clock input
1 —
4 —
71/72 (2)
Cyclone IV GX Transceiver Starter Board Reference Manual
12
12
Number
of I/Os
Special Pins
2–5