Altera Cyclone IV GX Reference Manual page 16

2–8
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 3)
Schematic Signal Name
FSML_D3
FSML_D4
FSML_D5
FSML_D6
FSML_D7
FSML_D8
FSML_D9
FSML_D10
FSML_D11
FSML_D12
FSML_D13
FSML_D14
FSML_D15
CONF_DONE_LED
MAX_ERROR
MAX_RESETn
MAX_CSn
PGM_CONFIG
PGM_LED0
PGM_LED1
PGM_SEL
SENSE_CSn
SENSE_SCK
SENSE_SDI
SENSE_SDO
SRAM_BWan
SRAM_BWbn
SRAM_CEn
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_CLK
Cyclone IV GX Transceiver Starter Board Reference Manual
Downloaded from Elcodis.com electronic components distributor
I/O EPM2210
Standard Pin Number
A7
B7
C8
A6
B6
A5
B5
C7
A4
B4
C4
C6
B3
T11
T8
M9
T12
2.5-V
R10
T9
R9
T10
J3
J1
J2
K1
C2
D2
E2
F2
F1
G2
G1
Table 2–6 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
EP4CGX15BF14
Pin Number
F9 FSML bus data
E13 FSML bus data
F10 FSML bus data
F11 FSML bus data
G9 FSML bus data
G10 FSML bus data
A12 FSML bus data
A11 FSML bus data
B11 FSML bus data
B10 FSML bus data
C11 FSML bus data
C12 FSML bus data
C8 FSML bus data
— FPGA configuration done LED
— FPGA configuration error LED
— MAX II reset push-button switch
L5 MAX II chip select
— Loads flash memory image identified by the
PGM LEDs
— Flash memory PGM select indicator 0
— Flash memory PGM select indicator 1
— Toggles the PGM_LED[0:1] sequence
— Power monitor chip select
— Power monitor serial peripheral interface (SPI)
clock
— Power monitor SPI data in
— Power monitor SPI data out
L4 FSML bus SSRAM byte write enable
M4 FSML bus SSRAM byte write enable
N6 FSML bus SSRAM chip enable
— FSML bus SSRAM address status controller
— FSML bus SSRAM address status processor
— FSML bus SSRAM address valid
L7 FSML bus SSRAM clock
Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Description
© March 2010 Altera Corporation