Flash - Altera Cyclone IV GX Reference Manual

2–24
Table 2–28. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board Reference
U12.85
U12.84
U12.83
U12.93
U12.94
U12.98
U12.89
U12.97
U12.92
U12.88
U12.31
U12.64
Table 2–29. SSRAM Component Reference and Manufacturing Information
Board
Reference
U12

Flash

Cyclone IV GX Transceiver Starter Board Reference Manual
Downloaded from Elcodis.com electronic components distributor
Description
Address status controller
Address status processor
Burst address advance
Byte lane a write enable
Byte lane b write enable
Chip enable
Clock
Chip enable
Chip enable
Global write enable
Burst sequence mode selection
Sleep enable
Table 2–29 lists the SSRAM component reference and manufacturing information.
Description
Standard Synchronous Pipelined
SCD, 1024 K × 18, 250 MHz
The flash interface consists of a single synchronous flash memory device, providing
128-Mb of memory with a 16-bit data bus. This device is part of the shared FSML bus
which connects to the flash memory, SRAM, LCD, and MAX II CPLD EPM2210
System Controller.
f
For more information about the flash memory map storage, refer to the
Transceiver Starter Kit User
Table 2–30 lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone IV GX device in terms of I/O setting and
direction.
Schematic Signal Name I/O Standard
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_BWan
SRAM_BWbn
SRAM_CEn
SRAM_CLK
SRAM_CE2
SRAM_CE3n
SRAM_GWn
SRAM_MODE
SRAM_ZZ
Manufacturing
Manufacturer Part Number
ISSI Inc. IS61VPS102418A-250TQL
Guide.
Chapter 2: Board Components
Memory
Cyclone IV GX Device
Pin Number
—
—
—
L4
M4
N6
2.5-V
L7
—
—
—
—
—
Manufacturer
Website
www.issi.com
Cyclone IV GX
© March 2010 Altera Corporation