Reset - Quectel RM502Q-GL Hardware Design

5g module
Hide thumbs Also See for RM502Q-GL:
Table of Contents

Advertisement

3.5. Reset

RESET_N is an asynchronous and active low signal (1.8 V logic level). Whenever this pin is active, the
modem will immediately be placed in a Power On Reset(POR) condition.
CAUTION: Triggering the RESET# signal will lead to loss of all data in the modem and the removal of
system drivers. It will also disconnect the modem from the network.
Table 7: Definition of RESET_N Pin
Pin No.
Pin Name
67
RESET_N
The module can be reset by pulling down the RESET_N pin for 200–700 ms. An open collector/drain
driver or button can be used to control the RESET_N pin.
Host
Figure 13: Reference Circuit of RESET_N with NPN Driving Circuit
RM502Q-GL_Hardware_Design
Description
Reset the module
Reset pulse
GPIO
R2
1k
DC Characteristics
V
= 2.1 V
IH(max)
V
= 1.3 V
IH(min)
V
= 0.5 V
IL(max)
RESET_N
Q1
NPN
R3
200-700ms
100k
5G Module Series
RM502Q-GL Hardware Design
Comment
Internally pulled up to 1.8 V
with a 100 kΩ resistor
Module
VDD 1.8V
R1
100k
67
Reset
Logic
28 / 77

Advertisement

Table of Contents
loading

Table of Contents