Configuration Pins - Quectel RM502Q-GL Hardware Design

3.13. Configuration Pins

RM502Q-GL provides four configuration pins, which are defined as below.
Table 20: Definition of Configuration Pins
Pin No. Pin Name
21 CONFIG_0
69 CONFIG_1
75 CONFIG_2
1 CONFIG_3
The following figure shows a reference circuit of these four pins.
Host
Note: The voltage level of VCC_IO_HOST depends on the host side and could be 1.8V or 3.3V.
Table 21: Configuration Pins List of M.2 Specification
Config_0 Config_1
(Pin 21) (Pin 69)
NC GND
RM502Q-GL_Hardware_Design
I/O
DO
DO
DO
DO
VCC_IO_HOST
R1 R2
10k 10k 10k
GPIO
GPIO
GPIO
GPIO
Figure 29: Recommended Circuit of Configuration Pins
Config_2
(Pin 75)
NC
Power Domain Description
0 NC internally
0 Connected to GND internally
0 NC internally
0 NC internally
R3 R4
10k
CONFIG_0
CONFIG_1
CONFIG_2
CONFIG_3
Config_3 Module Type and
(Pin 1) Main Host Interface
NC Quectel defined
5G Module Series
RM502Q-GL Hardware Design
Module
NM-0Ω
21
0Ω
69
NM-0Ω
75
NM-0Ω
1
Port
Configuration
N/A
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