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FULL_CARD_POWER_OFF#
RFFE_VIO_1V8
PCIE_CLKREQ_N
Figure 23: PCIe Power-on Timing Requirements of the Module
The following principles of PCIe interface design should be complied with, so as to meet PCIe V2.1
specification.
⚫
Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces.
⚫
It is important to route the PCIe differential signal traces in inner layer of the PCB, and surround the
traces with ground on that layer and with ground planes above and below.
⚫
For PCIe signal traces, the recommended maximum length for TX and RX differential data pairs is
less than 250 mm, and the intra-lane length matching of TX and RX differential data pairs is less than
0.7 mm (5 ps).
3.8.2. USB Version and PCIe Version
Begin with ES2 (Engineering Samples 2), RM502Q-GL supports USB version and PCIe only version
described as below:
USB version
⚫
Support all USB 2.0/3.1 features
⚫
Support MBIM/QMI/QRTR/AT
⚫
Support switch between USB and PCIe by AT command
USB is the default communication interface between RM502Q-GL module and a host. If PCIe interface is
desired, an AT command under USB interface mode could be used. For more details about the AT
command, please refer to document [2].
It is suggested that USB 2.0 interface could be reserved for firmware upgrade.
RM502Q-GL_Hardware_Design
Module power-on or insertion detection
VCC
t
power-on
RESET_N
System turn-on and booting
t
turn-on
PCIE_RST_N
PCIE_REFCLK
33 ms
68 ms
23 ms
T
PVPGL
T
PERST#-CLK
5G Module Series
RM502Q-GL Hardware Design
≥ 1.19 V
V
IH
> 50 ms
> 100 us
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