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t(cl)
SPI clock low-level time
t(mov)
SPI master data output valid time
t(mis)
SPI master data input setup time
t(mih)
SPI master data input hold time
NOTE
The module provides a 1.8 V SPI interface. A level translator should be used between the module and the host if
customers' application is equipped with a 3.3 V processor or device interface.
3.15. RGMII Interface
The module includes an integrated Ethernet MAC with an RGMII interface. Key features of the RGMII interface
are shown below:
⚫
Support IEEE 1588-2008, IEEE 802.1AS-2011 and 802.1-Qav-2009
⚫
Half/full duplex for 10/100/1000 Mbps
⚫
Support VLAN tagging
⚫
Can be used to connect to external Ethernet PHY like 88EA1512, or an external switch
Table 22: Pin Definition of RGMII Interface
Pin Name
RGMII_MD_IO
RGMII_MD_CLK
RGMII_RX_0
RGMII_RX_1
RGMII_CTL_RX
RGMII_RX_2
RGMII_RX_3
RGMII_CK_RX
AG521R-NA_QuecOpen_Hardware_Design
Pin No.
I/O
Description
10
IO
RGMII MDIO management data
11
DO
RGMII MDC management clock
13
DI
RGMII receive data bit 0
14
DI
RGMII receive data bit 1
15
DI
RGMII receive control
16
DI
RGMII receive data bit 2
17
DI
RGMII receive data bit 3
19
DI
RGMII receive clock
Automotive Module Series
AG521R-NA QuecOpen Hardware Design
9.0
-
-5.0
-
5.0
-
1.0
-
Comment
Power domain determined by
RGMII_PWR_IN
-
ns
5.0
ns
-
ns
-
ns
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