Quectel QuecOpen AG521R-NA Hardware Design page 57

SDIO_VDD 60
SDC1_DATA_0 49
SDC1_DATA_1 50
SDC1_DATA_2 51
SDC1_DATA_3 52
SDC1_CMD 48
SDC1_DATA_4 53
SDC1_DATA_5 55
SDC1_DATA_6 56
SDC1_DATA_7 58
SDC1_CLK 47
EMMC_RST 54
EMMC_PWR_EN 45
The following is a reference design of SDIO interface for eMMC application.
AG521R-NA_QuecOpen_Hardware_Design
PI SDIO power supply
IO SDIO data bit 0
IO SDIO data bit 1
IO SDIO data bit 2
IO SDIO data bit 3
IO SDIO command
IO SDIO data bit 4
IO SDIO data bit 5
IO SDIO data bit 6
IO SDIO data bit 7
DO SDIO clock
DO eMMC reset
eMMC power supply
DO
enable control
Automotive Module Series
AG521R-NA QuecOpen Hardware Design
Connect it to VDD_EXT.
1.8 V power domain for eMMC.
1.8 V power domain.
For eMMC configuration by default.
Can be configured to GPIO.
1.8 V power domain for eMMC.
1.8 V power domain.
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