Quectel QuecOpen AG521R-NA Hardware Design page 54

BT_UART_RXD 63
BT_UART_RTS 61
BT_UART_CTS 62
Table 15: Pin Definition of Debug UART Interface
Pin Name Pin No.
DBG_TXD 107
DBG_RXD 110
Table 16: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
The module provides 1.8 V UART interfaces. A level translator should be used if customers' application is
equipped with a 3.3 V UART interface. A level translator TXS0104E-Q1 provided by Texas Instruments (visit
http://www.ti.com for more information) is recommended. The following figure shows a reference design.
VDD_1V8
CTS
RTS
TXD
RXD
Another example with transistor translation circuit is shown as below. The circuit design of dotted line section can
refer to the design of solid line section, in terms of both module input and output circuit designs, but please pay
AG521R-NA_QuecOpen_Hardware_Design
DI BT UART receive
DI BT UART request to send
DO BT UART clear to send
I/O Description
DO Debug UART transmit
DI Debug UART receive
Min.
-0.3
1.17
0
1.35
VCCA
0.1 μF
OE
A1
Translator
A2
A3
A4
NC
Figure 22: Reference Circuit with Translator Chip
Automotive Module Series
AG521R-NA QuecOpen Hardware Design
Can be configured to GPIOs
Comment
1.8 V power domain.
1.8 V power domain.
Max.
0.63
2.1
0.45
1.8
VCCB
0.1 μF
GND
B1
B2
B3
B4
NC
Unit
V
V
V
V
VDD_MCU
CTS_MCU
RTS_MCU
TXD_MCU
RXD_MCU
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