Quectel QuecOpen AG521R-NA Hardware Design page 62

RGMII_MD_IO
RGMII_MD_CLK
RGMII_INT
RGMII_RST
RGMII_RX_0
RGMII_RX_1
RGMII_RX_2
RGMII_RX_3
RGMII_CTL_RX
RGMII_CK_RX
RGMII_TX_0
RGMII_TX_1
RGMII_TX_2
RGMII_TX_3
RGMII_CTL_TX
RGMII_CK_TX
RGMII_PWR_EN
RGMII_PWR_IN
Module
Figure 28: Reference Circuit of RGMII Interface with PHY Application
In order to enhance the reliability and availability of customers' application, please follow the criteria below in the
Ethernet PHY circuit design:
⚫
The I/O voltage of RGMII matches with that of PHY.
⚫
The voltage of RGMII_INT and RGMII_RST matches with the I/O voltage of PHY.
⚫
The typical power consumption of RGMII_PER_IN is 300 mA @ 1.8 V.
⚫
Keep RGMII data and control signals away from RF and VBAT traces.
⚫
Assure impedance of RGMII signals trace is 50 Ω ±20%.
⚫
The length difference among CK_TX, CTL_TX and TX_[0-3] is less than 2 mm.
⚫
The length difference among CK_RX, CTL_RX and RX_[0-3] is less than 2 mm.
⚫
TX bus (CK_TX to CTL_TX/TX_[0-3]) spacing or RX bus (CK_RX to CTL_RX/RX_[0-3]) spacing is larger
than two times of the line width.
⚫
Spacing between TX bus and RX bus is larger than 2.5 times of line width.
⚫
Spacing to all other signals is larger than three times of line width.
⚫
Resistors R7–R12 should be placed near the module. Resistor R1–R6 should be placed near the Ethernet PHY.
AG521R-NA_QuecOpen_Hardware_Design
R7 0R
R8 0R
R9 0R
R10 0R
R11 0R
R12 0R
RGMII_PWR_EN
RGMII_PWR_IN
Automotive Module Series
AG521R-NA QuecOpen Hardware Design
RGMII_VDDO
R13 R14 R15 R16
R1 0R
R2 0R
R3 0R
R4 0R
R5 0R
R6 0R
RGMII_VDDO
MDIO
MDC
INTN
RESETN
RXD0
RXD1
RXD2
RXD3
RXC
RCLK
TXD0
TXD1
TXD2
TXD3
RXC
RCLK
VDDO
Ethernet PHY
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