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RGMII_TX_0
RGMII_CTL_TX
RGMII_TX_1
RGMII_TX_2
RGMII_CK_TX
RGMII_TX_3
RGMII_PWR_EN
RGMII_PWR_IN
RGMII_INT
RGMII_RST
The following figure shows the simplified block diagram for Ethernet application.
RGMII
Module
MDIO
Figure 27: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of RGMII interface with PHY application.
AG521R-NA_QuecOpen_Hardware_Design
20
DO
RGMII transmit data bit 0
21
DO
RGMII transmit control
22
DO
RGMII transmit data bit 1
23
DO
RGMII transmit data bit 2
24
DO
RGMII transmit clock
25
DO
RGMII transmit data bit 3
Enable external LDO to supply
27
DO
power to RGMII_PWR_IN
Power input for internal RGMII
28
PI
circuit
29
DI
RGMII PHY interrupt output
31
DO
Reset output for RGMII PHY
RXD
TXD
MDIO
AG521R-NA QuecOpen Hardware Design
Ethernet
MDIP/N
PHY
Automotive Module Series
1.8 V power domain
1.8/2.5 V
power supply input.
If RGMII interface is not
used, please connect it to
VDD_EXT.
1.8 V power domain
CMC
60 / 92
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