Quectel QuecOpen AG521R-NA Hardware Design page 65

PCIE_CLKREQ
PCIE_WAKE
PCIE_RST
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX_M
PCIE_TX_P
PCIE_RX_M
PCIE_RX_P
COEX_UART_ RXD
COEX_UART_ TXD
BT_UART_TXD
BT_UART_RXD
BT_UART_RTS
BT_UART_CTS
PCM_SYNC
PCM_CLK
PCM_IN
PCM_OUT
WLAN_EN
BT_EN
WLAN_SLP_CLK
WLAN_PWR_EN1
WLAN_PWR_EN2
VDD_WIFI_VM
VDD_WIFI_VH
Module
Figure 29: Reference Circuit for Connection with WLAN&BT PHY
To ensure the signal integrity of PCIe interface, C1 and C2 should be placed close to the module. C3 and C4 should
be placed close to the PHY. The extra stubs of trace must be as short as possible.
AG521R-NA_QuecOpen_Hardware_Design
C1
100 nF
C2
100 nF
WLAN_PWR_EN1
WLAN_PWR_EN2
Automotive Module Series
AG521R-NA QuecOpen Hardware Design
VDD_EXT
R1 R2
100K 100K
C3
100 nF
C4
100 nF
PCIE_CLKREQ_N
PCIE_WAKE
PCIE_RST
PCIE_REFCLKP
PCIE_REFCLKM
PCIE_RXM
PCIE_RXP
PCIE_TXM
PCIE_TXP
COEX_UART_ TXD
COEX_UART_ RXD
BT_UART_RXD
BT_UART_TXD
BT_UART_RTS
BT_UART_CTS
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
WLAN_EN
BT_EN
SLEEP_CLK
VDD_WIFI_VM
VDD_WIFI_VH
WLAN&BT PHY
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