Infineon PSoC 62 Development Kit Manuals
Manuals and User Guides for Infineon PSoC 62 Development Kit. We have 1 Infineon PSoC 62 Development Kit manual available for free PDF download: Reference Manual
Infineon PSoC 62 Reference Manual (647 pages)
Brand: Infineon
|
Category: Single board computers
|
Size: 6.25 MB
Table of Contents
-
Overview19
-
Introduction20
-
Features20
-
Architecture22
-
Features34
-
Architecture35
-
Registers37
-
Features42
-
Architecture42
-
Wait States44
-
Features45
-
Architecture46
-
IPC Channel46
-
Features53
-
Architecture53
-
Fault Report54
-
Monitoring56
-
Interrupts61
-
Features61
-
Architecture62
-
Architecture81
-
Mpu90
-
Smpu90
-
Ppu91
-
Features102
-
Architecture103
-
Channels103
-
Descriptors106
-
Transfer Size110
-
DMA Controller111
-
Pending Triggers112
-
Output Triggers112
-
Status Registers112
-
DMA Performance113
-
Features115
-
Architecture116
-
Channels116
-
Descriptors118
-
Transfer Size123
-
DMAC Controller124
-
Channel Logic124
-
Output Triggers124
-
Features125
-
Architecture125
-
Instructions126
-
Hash Algorithms133
-
SHA1 and SHA2133
-
Sha3135
-
DES and TDES136
-
Aes139
-
Crc141
-
Prng143
-
Trng144
-
Vector Unit150
-
VU Register File152
-
Stack153
-
Memory Operands154
-
Datapath154
-
Status Register155
-
Instructions156
-
Instruction Set157
-
Features175
-
Architecture175
-
DAP Security177
-
DAP Power Domain177
-
ROM Tables178
-
Trace178
-
ACK Details180
-
JTAG Interface181
-
Registers185
-
Flash Memory186
-
Features186
-
Configuration186
-
Block Diagram186
-
Flash Geometry187
-
Flash Controller188
-
Wait State Count188
-
Power Modes188
-
CPU Caches189
-
Features190
-
Architecture190
-
SRAM Usage191
-
SROM API Library192
-
System Calls193
-
Infineon ID193
-
Blow Efuse Bit197
-
Read Efuse Byte198
-
Write Row199
-
Program Row201
-
Erase All203
-
Checksum205
-
Compute Hash207
-
Directexecute209
-
Erase Sector209
-
Soft Reset211
-
Erase Row212
-
Erase Subsector213
-
Generatehash214
-
Readuniqueid215
-
Checkfactoryhash216
-
Transitiontorma217
-
Boot Code221
-
Features221
-
ROM Boot221
-
Flash Boot232
-
Overview232
-
Using Flash Boot232
-
Header233
-
Code Segment233
-
Wait Window (14)237
-
Set up SP (17)238
-
Idle Loop (18)238
-
Efuse Memory240
-
Features240
-
Architecture240
-
Device Security242
-
Features242
-
Architecture242
-
Flash Security246
-
Features248
-
Architecture249
-
Power Supply250
-
Core Regulators250
-
Backup Domain252
-
Register List255
-
Features256
-
Architecture256
-
CPU Power Modes259
-
CPU Active Mode259
-
CPU Sleep Mode259
-
Backup Domain261
-
Reset State261
-
Off State261
-
Summary268
-
Register List269
-
Backup System270
-
Features270
-
Architecture271
-
Power Supply271
-
Clocking272
-
Calibration273
-
Reset273
-
Real-Time Clock273
-
Alarm Feature275
-
PMIC Control276
-
Backup Registers277
-
Register List277
-
Clocking System278
-
Features278
-
Architecture279
-
Clock Sources279
-
ECO Trimming280
-
Clock Generation281
-
Clock Trees287
-
Path Clocks287
-
Timer Clock289
-
Clk_Fast290
-
Clk_Peri290
-
Clk_Slow290
-
Reset System295
-
Features295
-
Architecture295
-
Power-On Reset297
-
Brownout Reset297
-
External Reset297
-
Register List299
-
O System300
-
Features300
-
Architecture301
-
Drive Modes303
-
GPIO-OVT Pins306
-
Interrupt310
-
Analog I/O313
-
LCD Drive313
-
Capsense313
-
Smart I/O314
-
Overview314
-
Block Components314
-
Clock and Reset315
-
Synchronizer316
-
Data Unit (DU)320
-
Routing324
-
Operation324
-
Registers326
-
Watchdog Timer327
-
Features327
-
Architecture327
-
Free-Running WDT328
-
Overview328
-
Watchdog Reset330
-
Overview332
-
MCDWT Reset339
-
MCWDT Interrupt339
-
Register List340
-
Features341
-
Architecture341
-
Register List345
-
Features348
-
Block Diagram349
-
Clocking350
-
Clock Gating350
-
Bus Speed Modes351
-
Power Modes352
-
Standby Mode352
-
SDIO Interrupt353
-
I/O Interface353
-
DMA Engine355
-
Enabling SDHC357
-
Card Detection357
-
Clock Setup360
-
Error Detection361
-
Features362
-
Architecture363
-
Buffer Modes363
-
FIFO Mode363
-
EZ Mode363
-
CMD_RESP Mode363
-
Clocking Modes364
-
Features365
-
Motorola SPI367
-
SPI Buffer Modes372
-
FIFO Mode372
-
EZSPI Mode373
-
Clock Modes378
-
SPI Master382
-
SPI Slave383
-
Median Filter384
-
SPI Registers384
-
Uart385
-
Features385
-
Smartcard Mode398
-
LIN Mode399
-
Irda Mode400
-
UART Registers400
-
Features401
-
Clock Stretching403
-
Bus Arbitration404
-
Write Transfer405
-
Read Transfer405
-
I2C Buffer Modes406
-
FIFO Mode406
-
EZI2C Mode407
-
Glitch Filtering411
-
I2C Registers416
-
SCB Interrupts417
-
SPI Interrupts418
-
UART Interrupts421
-
I2C Interrupts425
-
Features427
-
Architecture427
-
Tx and Rx Fifos429
-
Tx Command FIFO429
-
Tx Data FIFO430
-
Rx Data FIFO430
-
Command Mode431
-
XIP Mode431
-
Cache432
-
Arbitration432
-
Deselect Delay432
-
Cryptography433
-
Triggers443
-
Interrupts444
-
Sleep Operation444
-
Performance444
-
Overview445
-
Features445
-
Configuration446
-
Block Diagram446
-
Interrupt Lines446
-
Operation Modes447
-
Normal Operation448
-
CAN FD Operation448
-
Test Mode452
-
Timeout Counter454
-
RX Handling454
-
RX Fifos458
-
TX Handling462
-
Transmit Pause463
-
Tx Fifo464
-
TX Queue464
-
CAN Bit Timing467
-
CAN Bit Rates469
-
Message RAM470
-
Mram off484
-
TTCAN Operation484
-
Level 1485
-
Level 2485
-
Level 0485
-
TTCAN Timing486
-
Trigger Memory488
-
Stop Watch494
-
Level 0501
-
Synchronizing502
-
Setup Procedures504
-
Registers518
-
Features522
-
Architecture523
-
Clocking524
-
Clock Prescaling524
-
Count Input524
-
Trigger Inputs524
-
Trigger Outputs526
-
Interrupts527
-
PWM Outputs527
-
Power Modes528
-
Operation Modes528
-
Timer Mode529
-
Capture Mode536
-
Asymmetric PWM552
-
TCPWM Registers560
-
Features562
-
Architecture562
-
USB Bus Reset565
-
USB Packets566
-
Token Packet566
-
Data Packet571
-
Handshake Packet571
-
Retry Function571
-
Error Status572
-
Resume Operation578
-
Features581
-
Architecture582
-
Arbiter583
-
Memory Interface583
-
Arbiter Logic583
-
Operation583
-
Usb Phy584
-
Power Scheme584
-
VBUS Detection584
-
GPIO Mode Logic585
-
Endpoints585
-
Transfer Types586
-
RESUME Interrupt587
-
DMA Support589
-
USB Power Modes601
-
LCD Direct Drive603
-
Features603
-
Architecture603
-
Drive Modes604
-
PWM Drive604
-
Register List616
-
Analog Subsystem617
-
Features618
-
Architecture618
-
Startup Modes619
-
Registers620
-
Features621
-
Architecture622
-
Hysteresis625
-
Comparator Clock625
-
Register List626
-
Sar Adc627
-
Features627
-
Architecture628
-
SAR ADC Core628
-
Input Range629
-
Acquisition Time632
-
SAR ADC Clock632
-
SAR ADC Timing633
-
Sarmux633
-
Analog Routing634
-
Sarref635
-
Sarseq636
-
Averaging637
-
Range Detection638
-
Double Buffer638
-
SAR Interrupts638
-
Trigger640
-
SAR ADC Status640
-
Registers641
-
Features642
-
Architecture642
-
Algorithm644
-
Registers644
-
Capsense645
-
Revision History646
Advertisement