Standard Event Status Register - ILX Lightwave MPS-8033 Series User Manual

Standard Event Status Register

Standard Event Status is an 8−bit register/enable−register pair with this structure:
Logical OR
To Bit 5, Status Byte Register
Bit Reference:
0− Operation Complete
1− N/A
2− Query Error
3− Device Dependent Error
The Standard Event Status Enable Register allows you to control which events in the Standard
Event Status Register can set bit 5 in the status byte register. The format of this register pair is
defined by GPIB standards.
Standard event status indicates the FIRST occurrence, and does not change except when reset.
The 8033 starts at power ON with the standard event status register set to all zeros. Querying the
Standard Event Status Register resets its contents to zeros.
Bit 0 is key to an interrupt−driven control program, because it allows you to generate a service
request (SRQ) when current operations are completed before making a measurement. To generate
an operation complete SRQ, follow this sequence:
• *ESE 1˙Enable bit 0 of the Standard Event Status Enable Register.
• *SRE 32˙Enable bit 5 of the Service Request Enable Register.
• *OPC˙Set bit 0 in the Event Status Register when all pending overlapped commands
have been completed.
Related commands: (See Chapter 4, Command Reference for details).
• *ESR?˙Query the contents of the Standard Event Status Register.
• *ESE <nrf>˙Set an enable mask in the Standard Event Status Enable Register.
• *ESE?˙Query the Standard Event Status Enable Register mask settings.
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7 6 5 4 3 2 1 0
Standard Event Status Register
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7 6 5 4 3 2 1 0 Standard Event Status Enable Register
4− Execution Error
5− Command Error
6− User Request
7− Power On
R E M O T E O P E R A T I O N
Status Reporting
3
C H A P T E R
29
MPS-8033 !