Reset Sources; Boot Option; Table 6. X2 Crystal Related Solder Bridge Settings - ST STM32L4R9I-EVAL User Manual

UM2248
Solder
bridge
SB49
Solder
bridge
SB52
SB53
6.7

Reset sources

The reset signal of the STM32L4R9I-EVAL board is active LOW.
Sources of reset are listed below:
•
reset button B2
•
CN17 JTAG/SWD connector, CN12 ETM trace connector, CN11 STDC14 connector
and CN15 TAG connector (reset from debug tools)
•
reset through pin 27 of CN6 extension connector (reset from daughterboard)
• embedded ST-LINK/V2-1
6.8

Boot option

After reset, the STM32L4R9AII6 MCU boot is available from the following embedded
memory locations:
•
main (user, non-protected) Flash memory
• system (protected) Flash memory
•
RAM, for debugging
Table 5. X1 crystal related solder bridge settings (continued)
Setting
Default setting.
Open
PC15 OSC32_OUT terminal is not routed to the CN5 extension
connector. X1 is used as the clock reference.
PC15 OSC32_OUT is routed to the CN5 extension connector.
Closed Resistor R49 must be removed, for the X1 quartz circuit not to
disturb clock reference on the daughterboard.

Table 6. X2 crystal related solder bridge settings

Setting
Default setting.
Open
PH0 OSC_IN terminal is not routed to the CN5 extension
connector. X2 is used as the clock reference.
PH0 OSC_IN is routed to the CN5 extension connector. Resistor
Closed R61 must be removed, in order not to disturb clock reference or
source on the daughterboard.
Default setting.
Open
PH1 OSC_OUT terminal is not routed to the CN5 extension
connector. X2 is used as the clock reference.
PH1 OSC_OUT is routed to the CN5 extension connector. Resistor
Closed R65 must be removed, in order not to disturb clock reference or
source on the daughterboard.
UM2248 Rev 4
Hardware layout and configuration
Configuration
Configuration
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