Power Supply; Table 3. Setting Of Configuration Elements For Cn12 Trace Connector - ST STM32L4R9I-EVAL User Manual

UM2248
Table 3 shows the setting of configuration elements to shunt PE2, PE5, and PE6 MCU ports
to the CN12 connector, to use them as debug trace signals.
Element
R53
SB56
R209
SB59
R211
SB60
Warning: Enabling the CN12 trace outputs through hardware modifications described in
Table 3 results in reducing the memory address bus width to 20 address lines and so the
addressable space to 1 Mword of 16 bits. As a consequence, the onboard SRAM and NOR
Flash memory usable capacity is reduced to 16 Mbits.
6.5

Power Supply

The STM32L4R9I-EVAL board is designed to be powered from 5 V DC power source. It
incorporates a precise polymer Zener diode (Poly-Zen) protecting the board from damage
due to the wrong power supply. One of the following four 5 V DC power inputs is usable with
an appropriate board configuration:
•
Power jack CN18 marked PSU_DC5V on the board. A jumper must be placed in E5V
location of JP11. The positive pole is on the center pin as illustrated in
•
Micro-B USB receptacle CN21 of ST-LINK/V2-1 provides up to 500mA to the board.
Offering enumeration feature described in
•
Micro-AB USB receptacle CN3 of USB OTG interface marked USB OTG_FS on the
board, supplies up to 500mA to the board.
•
Pin 39 of CN5 and Pin 39 of CN6 extension connectors for a custom daughterboard,
marked D5V on the board.
No external power supply is provided with the board.
LD7 red LED turns on when the voltage on the power line marked as +5 V is present. All
supply lines required for the operation of the components on STM32L4R9I-EVAL are
derived from that +5 V line.
Table 4 describes the setting of all jumpers related to powering the STM32L4R9I-EVAL and
its extension board. VDD_MCU is STM32L4R9AII6 digital supply voltage line. It is possible to
drive the boards with either fixed 3.3 V or with an adjustable voltage regulator controlled by
RV3 potentiometer and producing a range of voltages between 1.71 V and 3.6 V.

Table 3. Setting of configuration elements for CN12 trace connector

Setting
R53 in
SB56 open
R53 out
SB56 closed
R209 in
SB59 open
R209 out
SB59 closed
R211 in
SB60 open
R211 out
SB60 closed
Default setting.
PE2 connected to memory address line A23.
PE2 connected to Trace_CK on CN12. A23 pulled down.
Default setting.
PE5 connected to memory address line A21.
PE5 connected to Trace_D2 on CN12. A21 pulled down.
Default setting.
PE6 connected to memory address line A22.
PE6 connected to Trace_D3 on CN12. A22 pulled down.
Section
UM2248 Rev 4
Hardware layout and configuration
Configuration
Figure
6.5.1.
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