Service Request: Enable And Event Registers - TDK-Lambda GENESYS GEN 2400W Series Technical Manual

7.8.3

Service Request: Enable and Event Registers

The Conditional Registers are continuously monitored. When a change is detected in a register bit which is
enabled, the power supply will generate an SRQ message.
The SRQ message is: "!nn" terminated by CR, where the "nn" is the power supply Address. The SRQ will be
generated either in Local or Remote mode. Refer to Tables 7-9 to 7-12 for details of the Enable and Event
Registers.
7.8.3.1 Fault Enable Register
The Fault Enable Register is set to the enable fault SRQ's.
Enable
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2 Over-Temperature
3 FOLDback
4
OverVoltage
5 Shut-Off
6 Output OFF
7(MSB)
Enable
7.8.3.2 Fault Event Register
The Fault Event will set a bit if a condition occurs and it is Enabled. The register is cleared when FEVE?, CLS or
RST commands are received.
Enable
BIT
bit name
0 (LSB) Spare bit
1 AC Fail
2
Over-Temperature
3 FOLDback
4 Over-Voltage
5
Shut-Off
6 Output OFF
7(MSB) Enable
Fault symbol Bit Set condition
SPARE
AC
OTP
User command:
"FENA nn" where
FOLD
"nn" is
hexadecimal
OVP
SO
OFF
ENA
Table 7-9: Fault Enable Register
Fault symbol Bit Set condition
SPARE
AC
Fault condition
OTP occurs and it is
enabled.
FOLD
The fault can set a
bit, but when the
OVP
fault clears the bit
SO
remains set.
OFF
ENA
Table 7-10: Fault Event Register
69
83-517-000 Rev. A
Bit reset condition
User command: "FENA nn"
where "nn" is hexadecimal. If
nn="00", no fault SRQ's will be
generated.
Bit reset condition
Entire Event Register is
cleared when user sends
"FEVE?" command to read
the register.
"CLS" and AC Input power-up
also clear the Fault Event
Register. (The Fault Event
Register is not cleared by the
RST command)