Terminal Connections; Data Format; Basic Registers; Input Data Bit Assignment - Toshiba V Series User Manual

Terminal Connections

Data format

(1) Basic registers

Change detection status and Input data
XWn
XWn+1
XWn+2
XWn+3
[Rising edge detection status bit assignment]
Bit
US: When corresponding bit of input data changes from OFF to ON, it sets to '1'.
[Falling edge detection status bit assignment]
Bit
LS: When corresponding bit of input data changes from ON to OFF, it sets to '1'.

[Input data bit assignment]]

Bit
This register reflects the current input signal status.
When the interrupt enable flag is set to ON (DE='1') and the rising edge detection is selected
(UE='1'), the CD633 sets corresponding bit of the change detection status register (US) and
generates interrupt to the controller at the time of input signal change from OFF to ON.
As same manner, when the falling edge detection is selected (LE='1'), the CD633 generates
interrupt at the time of input signal change from ON to OFF.
If both UE and LE are set '1', the interrupt is generated at the time of both change from OFF
to ON and from ON to OF
The change detection status is cleared to '0', when the controller is read the change
detection status and input data. Therefore make the application program to read the change
detection status and input data (3 words) at the same time by the direct I/O instruction, in the
I/O interrupt program.
6F8C0836
1
1
2
3
3
4
5
5
6
7
7
8
9
9
10
11
B
12
13
D
14
15
F
16
17
COM
18
PS
S2T S2
%IWn Rising edge detection status
%IWn+1 Falling edge detection status
%IWn+2 Input data
%IWn+3 No use (reserved)
F E D C B
US US US US US US US US US US US US US US US US
F E D C B
LS LS LS LS LS
F E D C B
F E D C B
0
: DC power supply
PS
2
4
6
8
: Input switch
A
(solid-state device only)
C
E
COM
Description
A 9 8 7 6
A 9 8 7 6
LS LS LS LS LS
A 9 8 7 6
A 9 8 7 6
2.3 I/O Module Specification
or
5 4 3 2 1 0
5 4 3 2 1 0
LS LS LS LS LS LS
5 4 3 2 1 0
5 4 3 2 1 0
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