The processor core voltage is 2.5V, and the external interface operates at
3.3V. The input clock to the DSP is a 16-MHz through-hole oscillator.
Footprints are provided on the board for a surface-mount oscillator or a
through-hole crystal. The speed at which the core operates is determined
by the configuration of the multiplication factor switch (
the state of the
(JP7)" on page 3-9
page
3-10.) By default, the processor core runs at 160 MHz.
External Memory Interface (EMI)
The External Memory Interface (EMI) is connected to a 512K x 8-bit
Flash memory. This memory is connected to the boot memory select
(
) pin and the memory select 0 (
~BMS
to be used to boot the processor as well as store information during nor-
mal operation. Refer to
about the location of the Flash memory in the processor's memory map.
All of the address, data, and control signals are available externally via two
off-board connectors. The pinout of the EMI connectors (
shown in "Schematics" on page B-1.
The upper 8-bits of the data bus (
ble flag pins.
Host Port Interface (HPI)
The Host Port Interface (HPI) signals are brought to an unpopulated off
board connector
The pinout of the host port connector (
page
B-1.
ADSP-2191 EZ-KIT Lite Evaluation System Manual
jumper (
BYPASS
JP7
and
"DSP Clock Multiplier Select Switch (SW4)" on
"Memory Map" on page 2-2
. This allows the HPI to interface to a user application.
P12
EZ-KIT Lite Hardware Reference
). (See
"Bypass Mode Select Switch
) pin, allowing the Flash memory
~MS0
) can also be used as programma-
D15–D8
) is shown in
P12
) at reset and
SW4
for information
,
) is
P10
P11
"Schematics" on
3-3
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